Commit Graph

39 Commits

Author SHA1 Message Date
c13ca614ef libcortex_a9/mutex: use AcqRel for CAS operations 2020-08-24 15:24:20 +08:00
511c906d4d libcortex_a9/uncached: fixed mmu setting 2020-08-20 13:01:49 +08:00
283bc9b810 libcortex_a9: added L2 cache 2020-08-20 13:01:17 +08:00
fa07bdb681 libcortex_a9/mmu: share ocm3.
This fixes issue #54.
2020-08-07 15:10:38 +08:00
3958953ceb libcortex_a9/sync_channel: added drop_elements function. 2020-08-05 15:29:28 +08:00
25c6d5eeaa Changes usage of sev/wfe to spinlock functions. 2020-08-04 13:54:19 +08:00
9e97102e12 libcortex_a9: implemented semaphore. 2020-08-04 13:34:08 +08:00
b65606f2d0 libcortex_a9/sync_channel: added reset. 2020-08-03 15:50:31 +08:00
12669124a4 libcortex_a9/mutex: added interrupt critical section mask. 2020-08-03 12:35:17 +08:00
8f0a6bd5ea libsupport_zynq/abort: restart core1 main on core1 IRQ#0. 2020-08-03 12:35:17 +08:00
c1f61b5673 libcortex_a9/boot: enable IRQ on reset. 2020-08-03 12:35:17 +08:00
b099c56569 libcortex_a9/sync_channel: new version compiled. 2020-07-28 12:36:16 +08:00
074438c3c7 libcortex_a9: added try_lock for mutex. 2020-07-15 16:44:01 +08:00
191abf6b8f mpidr: wrap with proper bitfield getters
Prevents callers from dealing with CORE_MASK.
2020-07-08 00:04:54 +02:00
90e33f688a FPU: moved enable function to zc706 2020-07-03 16:02:34 +08:00
c6fa18344e uncached: disable cachable/bufferable 2020-06-26 22:32:49 +02:00
5c69bbdad6 mmu: fix L1Table.update() flush 2020-06-26 22:31:56 +02:00
d96343c249 uncached: refactor into UncachedSlice 2020-06-18 01:28:25 +02:00
ae739146c5 cache: add the required barriers 2020-06-18 01:27:34 +02:00
f50018092c mmu: add early memory barrier to L1Table.update() 2020-06-18 01:27:34 +02:00
7c4d390ce4 libcortex_a9: start Uncached 2020-06-18 01:27:34 +02:00
6761575b30 mmu: add L1Table.update() 2020-06-18 01:27:34 +02:00
aebce435e2 mmu: switch bufferable=1 (writeback) for DDR pages 2020-06-18 01:27:34 +02:00
5332587de6 Changed mutability 2020-06-10 12:54:50 +08:00
66cd0c7630 libcortex_a9: allow access for full 1GB of DDR 2020-05-09 02:35:39 +02:00
0d4d021b1b clean up 2020-05-01 01:17:53 +02:00
2c756ba32e libcortex_a9: migrate from asm! to llvm_asm! to avoid future breakage 2020-05-01 01:11:35 +02:00
008a995429 libcortex_a9: remove mmu::l1_table alignment through linker script
no longer needed, #[repr(16384)] works now
2020-04-30 03:38:27 +02:00
282b4dc69a link.x: reduce alignment, use all remaining OCM for .stack 2020-04-28 02:50:07 +02:00
614b1ef350 regs: add MVBAR and HVBAR 2020-04-27 12:49:18 +08:00
fefd2a4ceb regs: add VBAR 2020-04-27 12:34:15 +08:00
b26327e474 typo 2020-04-13 10:39:38 +08:00
0000575ce0 libasync: add async_send/async_recv methods 2020-04-13 01:24:37 +02:00
6fd6f429fe libcortex_a9: impl Iterator for sync_channel::Receiver 2020-04-09 02:56:54 +02:00
e54edbf32d libcortex_a9: add sync_channel 2020-04-09 02:49:24 +02:00
64771bf233 libcortex_a9: revamp cache maintenance 2020-04-09 00:18:23 +02:00
965a00801e libcortex_a9: set DDR pages non-bufferable to fix eth dma 2020-03-31 01:09:28 +02:00
1e5fe1b836 regs: add more #[inline] annotations
reduces .text size by 740 bytes
2020-02-03 00:50:13 +01:00
cf1983e543 split into lib{register, cortex_a9, board_zynq, board_zc706} crates 2019-12-17 23:35:58 +01:00