Commit Graph

152 Commits

Author SHA1 Message Date
9b4f07f37c zynq::ddr, main: parameters, memtest 2019-10-25 23:19:34 +02:00
e61d1268ac zynq::slcr: doc, fix 2019-10-25 23:18:18 +02:00
a4d3360a70 zynq::slcr: implement Display for PllStatus 2019-10-25 20:38:10 +02:00
838434cdec zynq::ddr: wait for init 2019-10-25 19:15:22 +02:00
4cf5283ba8 zynq::ddr: implement reset_ddrc(), add to main 2019-10-24 01:39:14 +02:00
a8886de067 zynq::ddr: implement configure_iob() 2019-10-24 01:24:12 +02:00
afda48e3fe zynq::ddr: add clock_setup(), calibrate_iob_impedance() 2019-10-22 01:25:35 +02:00
c046bbf8a2 move slcr, clocks, uart, eth into src/zynq/ 2019-10-21 22:19:03 +02:00
9d725bcf0f zynq::ddr: init with clock setup 2019-10-21 22:12:10 +02:00
58cf9833cc slcr: implement PllCfg and DdrClkCtrl 2019-10-21 22:10:51 +02:00
83b8bb096a add zynq::axi_gp 2019-10-19 01:46:43 +02:00
b541160f38 add zynq::axi_hp 2019-10-18 23:46:00 +02:00
Björn Stein
1804c4c6e8 cortex_a9: add proper L1 cache invalidation 2019-10-18 00:11:51 +02:00
Björn Stein
d87b874b21 eth: add memory barriers, reorder access 2019-10-18 00:04:22 +02:00
Björn Stein
9053166acc eth: increase desc list safety 2019-10-18 00:03:17 +02:00
4e9c38527e rm debug, delint 2019-09-29 03:01:24 +02:00
a76214cb9d eth: split into Eth and EthInner 2019-09-29 02:58:17 +02:00
0f6bc68d1f eth: prepare link change detection 2019-09-29 02:30:03 +02:00
378755a0ce main: bump RX_LEN/TX_LEN to 2 2019-09-29 01:40:38 +02:00
644cc64524 eth: align DescEntries 2019-09-29 01:39:12 +02:00
4c62ce0dad main: restrict eth buffers to 1 each 2019-08-19 02:21:36 +02:00
9c73cf130d eth: wait for link 2019-08-19 02:21:02 +02:00
45ed5f6c5b abort handlers: replace panic with infinite loop 2019-08-19 01:18:12 +02:00
d11e581862 main: setup smoltcp
still panics, leading to a DataAbort
2019-08-19 01:18:12 +02:00
3a5ed0aac6 eth: add smoltcp support 2019-08-19 01:18:12 +02:00
5603766c5d eth: enable csum offloading
should prevent FCS errors
2019-08-19 01:12:52 +02:00
43c3f3e4a6 eth: fix tx_clock magnitude bug
Ethernet TX now works!
2019-08-18 22:52:05 +02:00
4bc1d21ae9 eth: rm obsolete TODO 2019-08-18 22:44:33 +02:00
bfb3a00a4e eth: derive proper mdc_clk_div from clocks 2019-08-18 22:43:56 +02:00
b8818863c4 read clocks 2019-08-17 03:20:04 +02:00
1f9ad5ff62 delint 2019-08-11 00:56:54 +02:00
b7690c9702 fix UART_REF_CLK
started to become garbled.
2019-08-07 00:27:01 +02:00
d001593a36 rm bcmp 2019-08-06 22:03:23 +02:00
2db35d063f define bcmp
other solution might be defining a non-linux target
2019-08-06 14:15:44 +02:00
b9c233b05b compile fixes 2019-07-01 00:15:17 +02:00
d6b2321fee eth: fix mio_pin setup 2019-06-29 00:00:22 +02:00
9ab40daca2 eth: setup_gem0/1_clock() 2019-06-25 21:50:38 +02:00
5823d90db1 phy: implement control, status, reset 2019-06-25 21:48:47 +02:00
e6827a81f3 eth tx: set net_ctrl.start_tx on sending 2019-06-25 01:46:29 +02:00
374686fd3e eth tx: set last_buffer flag 2019-06-24 02:15:11 +02:00
ce74fe7299 eth: prepare tx 2019-06-22 01:39:44 +02:00
ec5dda4d0a eth: add const MTU 2019-06-22 01:34:17 +02:00
6757ceb76c eth rx: error handling 2019-06-22 01:20:18 +02:00
a4be03bee9 rx: PktRef 2019-06-21 01:19:04 +02:00
80f003b2c6 stdio: add print 2019-06-21 01:18:24 +02:00
e5881a14ad eth rx: descriptors/buffers as refs
avoid moving these after their addresses have been written to the qbar
2019-06-21 00:58:18 +02:00
d65398205f add a println! for convenience 2019-06-20 00:30:18 +02:00
b3b65f9b74 eth: find Phy 2019-06-19 00:21:17 +02:00
54d0f3583d eth: fix io configuration
phy detection now works
2019-06-18 23:10:35 +02:00
1634513bc7 mmu: align l1_table 2019-06-18 19:18:47 +02:00
9bebfb49bc begin MMU implementation 2019-06-17 03:32:10 +02:00
69b65b5f72 cortex_a9 regs: allow defining bit fields 2019-06-17 01:36:11 +02:00
1e16beb707 cortex_a9::regs: use crate::regs interface 2019-06-12 00:20:23 +02:00
81a892b618 eth: recv_next() 2019-06-10 02:44:29 +02:00
f92ea3b99d eth: start_tx 2019-06-09 20:28:33 +02:00
f07a541c99 eth: model rx/tx state with type parameters 2019-06-09 20:10:41 +02:00
74bd81f87f eth: add safety asserts 2019-06-09 02:23:37 +02:00
824e91e6cb eth: rx/tx desc list, start_rx 2019-06-09 01:02:10 +02:00
2d7fed6c59 link again compiler_builtins
required for memset etc
2019-06-09 01:00:58 +02:00
d447f1cc45 main: probe for PHYs 2019-06-04 23:50:11 +02:00
b9ca9324f0 eth: fix initialization 2019-06-04 23:48:33 +02:00
6d15b82a3e cortex_a9::regs: init U bit for unaligned access 2019-06-04 23:47:23 +02:00
acf995d7da soft_reset: rm unreachable! 2019-05-31 00:19:20 +02:00
bf4f5108f4 main: add UART_RATE 2019-05-31 00:19:01 +02:00
2df74cc055 add static exception handling 2019-05-30 20:30:19 +02:00
b13bf72c17 eth: begin phy communication 2019-05-30 02:42:42 +02:00
5b15bb5c0a main: make boot_core0() naked 2019-05-30 02:41:44 +02:00
c0610ad66a slcr: init gem* rclk/clk 2019-05-30 02:26:19 +02:00
ee7ae7f7cc slcr: add soft_rst() 2019-05-30 00:24:51 +02:00
b961526b97 uart: remove type conversion from baud_rate_gen 2019-05-30 00:22:45 +02:00
a645d13f4b add uart panic handler 2019-05-28 00:28:35 +02:00
75bb755327 extend linker script 2019-05-27 22:38:10 +02:00
d10ffe9eb9 eth: setup mio_pins, configure net_cfg 2019-05-25 03:06:39 +02:00
51c39f032e run with the cora z7-10 2019-05-25 02:38:48 +02:00
b3da0e4c93 slcr: define all mio_pin regs, typed io_type 2019-05-25 02:34:58 +02:00
6bf210366a regs: properly emit doc_comments 2019-05-24 23:49:49 +02:00
56c2f1d833 eth: add net_status, phy_maint registers 2019-05-24 00:20:59 +02:00
ad77e3dc04 eth: add net_cfg register 2019-05-24 00:06:29 +02:00
402b8c9ab1 eth: no unsafe, note, add qbar register fields 2019-05-23 23:18:36 +02:00
1033648c3e add l1_cache_init() 2019-05-23 19:05:06 +02:00
179c617904 add register_bits_typed! macro 2019-05-23 18:29:05 +02:00
785e726661 RegisterW/RegisterRW: required &mut self for safety 2019-05-23 18:01:18 +02:00
62ca26fa71 slcr: abstract with RegisterBlock 2019-05-23 17:52:06 +02:00
fd7fd0db14 main: rm unused feature #![feature(global_asm)] 2019-05-23 16:06:41 +02:00
ea62d4fdec uart: make baudrate configurable, run at 115,200 baud 2019-05-23 15:50:53 +02:00
15883293ac uart: use div_round_closest in baud_rate_gen 2019-05-23 15:37:07 +02:00
7428fec200 uart: add more channel_sts flags, wait for tx_fifo_empty() before sending 2019-05-23 15:36:34 +02:00
673d585d2f uart: extend regs 2019-05-22 01:42:24 +02:00
b296fc1d7f uart: add baud_rate_gen 2019-05-22 01:42:00 +02:00
43b6d3acd0 uart: wait for reset 2019-05-21 02:53:59 +02:00
47ec0116a9 use uart1 with more configuration 2019-05-21 01:30:54 +02:00
5d02fe5c95 slcr: with_slcr() for unlock/lock 2019-05-21 01:30:17 +02:00
351d18c10f add register_at! macro 2019-05-20 23:01:50 +02:00
c88374eab1 fix SP init 2019-05-20 01:21:22 +02:00
b754581452 eth: add regs and init 2019-05-07 19:28:33 +02:00
7872e00182 uart: move logic outside regs 2019-05-07 17:46:37 +02:00
275f297309 uart: impl fmt::Write 2019-05-07 16:45:31 +02:00
ca9b10dce8 refactor regs macros for RO/WO/RW access 2019-05-07 00:32:45 +02:00
1e540a1175 replace #[repr(packed)] with #[repr(C)]
avoids warnings regarding unsafe behaviour
2019-05-07 00:05:38 +02:00
fdc6c38de6 enable_uart0(): add srcsel 2019-05-07 00:01:43 +02:00