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78caca1f04
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zynq::flash: setup additional signals
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2019-11-28 03:22:26 +01:00 |
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5642feb824
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zynq::flash: add missing config bits to enable addressing mode
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2019-11-28 03:02:51 +01:00 |
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a199a5dc7d
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zynq::flash: add more setup
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2019-11-23 01:59:24 +01:00 |
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3180f1c3f7
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zynq::flash: begin driver implementation
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2019-11-21 00:14:09 +01:00 |
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8037042040
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zynq::slcr: implement boot_mode bits
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2019-11-20 21:31:54 +01:00 |
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ef6d0ff3f1
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boot: reset core1 before start
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2019-11-18 00:38:03 +01:00 |
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49901d1b8a
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boot: prepare core1 bootup
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2019-11-15 23:59:01 +01:00 |
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Björn Stein
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4a1d0fc0c3
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zynq::mpcore: add register definitions
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2019-11-14 02:11:58 +01:00 |
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3279aab961
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main: refactor into abort, panic, ram
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2019-11-11 02:46:18 +01:00 |
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92c274348f
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zynq::eth: enable checksum offload
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2019-11-11 01:42:41 +01:00 |
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3eb7fce572
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delint
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2019-11-11 01:42:38 +01:00 |
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3496755406
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update rust + smoltcp
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2019-11-11 00:28:46 +01:00 |
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959bf8a245
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zynq::eth: don't check_link_change if link already established
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2019-11-11 00:08:48 +01:00 |
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4d3b2ac7e5
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zynq::ddr: use different data_bus_width for targets
DDR still works only on the zc706, not on the cora z7-10.
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2019-11-11 00:06:35 +01:00 |
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cae02947bc
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zynq::eth: remove all memory barriers
They were not the solution.
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2019-11-10 23:52:55 +01:00 |
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afd96bd887
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zynq::clocks: unlock slcr in enable_io()
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2019-11-07 00:13:50 +01:00 |
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261455877d
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zynq::ddr: fix DDR 3x/2x setup, print clocks
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2019-11-07 00:13:50 +01:00 |
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ff96bf903b
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zynq::ddr: only enable_ddr if no clock yet
that's only an issue for the cora z7
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2019-11-07 00:13:50 +01:00 |
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d2df5652d0
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Revert "zynq: replace unnecessary slcr::unlocked with new"
This reverts commit 6bee1f44f4.
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2019-11-07 00:13:50 +01:00 |
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eb56dda44f
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zynq::slcr::unlocked: fix comment
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2019-11-07 00:13:50 +01:00 |
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74c43b3477
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zynq::eth::tx: clear entry.word1 for each packet
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2019-11-04 02:31:40 +01:00 |
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99a00e019b
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zynq::eth: implement phy::extended_status, set clock for link speed
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2019-11-04 02:30:00 +01:00 |
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961e2e1dd0
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zynq::{ddr, eth}: fix clock divisor calculation
off-by-one, didn't change behavior.
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2019-11-03 02:23:16 +01:00 |
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04e816d99e
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zynq::slcr: fix a bitfield index
that didn't solve our problems.
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2019-11-03 02:01:42 +01:00 |
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6bee1f44f4
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zynq: replace unnecessary slcr::unlocked with new
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2019-10-31 20:48:07 +01:00 |
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5c62716a99
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zynq::eth: switch rx and tx descriptor words to vcell
vcell can be initialized cleanly.
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2019-10-31 03:15:13 +01:00 |
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e248d3d3b1
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zynq::ddr: optimize memtest
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2019-10-31 01:32:45 +01:00 |
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91bab76ab6
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zynq::ddr: fix usable ram size
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2019-10-31 01:27:49 +01:00 |
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ceeaa6427e
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zynq::ddr: fix typo
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2019-10-28 23:58:25 +01:00 |
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fc39885d3b
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zynq::ddr: fix clock setup
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2019-10-28 00:43:09 +01:00 |
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f199ac68b4
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zynq::ddr: don't overwrite slcr.ddr_pll_ctrl
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2019-10-27 22:54:34 +01:00 |
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637bb35f43
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zynq::ddr: fix memtest progress calculation
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2019-10-27 20:38:35 +01:00 |
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85bd506132
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zynq::ddr: parameters
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2019-10-27 20:38:06 +01:00 |
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27114aec62
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zynq::ddr: fix PLL_FDIV_LOCK_PARAM usage
this seems to make DDR RAM work.
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2019-10-27 20:30:56 +01:00 |
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9b4f07f37c
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zynq::ddr, main: parameters, memtest
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2019-10-25 23:19:34 +02:00 |
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e61d1268ac
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zynq::slcr: doc, fix
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2019-10-25 23:18:18 +02:00 |
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a4d3360a70
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zynq::slcr: implement Display for PllStatus
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2019-10-25 20:38:10 +02:00 |
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838434cdec
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zynq::ddr: wait for init
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2019-10-25 19:15:22 +02:00 |
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4cf5283ba8
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zynq::ddr: implement reset_ddrc(), add to main
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2019-10-24 01:39:14 +02:00 |
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a8886de067
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zynq::ddr: implement configure_iob()
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2019-10-24 01:24:12 +02:00 |
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afda48e3fe
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zynq::ddr: add clock_setup(), calibrate_iob_impedance()
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2019-10-22 01:25:35 +02:00 |
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c046bbf8a2
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move slcr, clocks, uart, eth into src/zynq/
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2019-10-21 22:19:03 +02:00 |
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9d725bcf0f
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zynq::ddr: init with clock setup
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2019-10-21 22:12:10 +02:00 |
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83b8bb096a
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add zynq::axi_gp
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2019-10-19 01:46:43 +02:00 |
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b541160f38
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add zynq::axi_hp
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2019-10-18 23:46:00 +02:00 |
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