forked from M-Labs/zynq-rs
parent
4565a75766
commit
fa07bdb681
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@ -32,23 +32,23 @@ SECTIONS
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*(.bss .bss.*);
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. = ALIGN(4);
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__bss_end = .;
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} > OCM
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} > OCM3
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.stack1 (NOLOAD) : ALIGN(8) {
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__stack1_end = .;
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. += 0x200;
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__stack1_start = .;
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} > OCM
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} > OCM3
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.stack0 (NOLOAD) : ALIGN(8) {
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__stack0_end = .;
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. = ORIGIN(OCM) + LENGTH(OCM) - 8;
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. = ORIGIN(OCM3) + LENGTH(OCM3) - 8;
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__stack0_start = .;
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/* unused heap0 to prevent the linker from complaining*/
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__heap0_start = .;
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__heap0_end = .;
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} > OCM
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} > OCM3
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/DISCARD/ :
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{
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@ -338,7 +338,7 @@ impl L1Table {
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/* 0xfff00000 - 0xffffffff (256K OCM when mapped to high address space) */
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self.direct_mapped_section(0xfff, L1Section {
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global: true,
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shareable: false,
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shareable: true,
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access: AccessPermissions::FullAccess,
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tex: 0b100,
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domain: 0,
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