forked from M-Labs/zynq-rs
zynq::flash: enable big endian mode
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parent
f3676c945a
commit
aab82f6843
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@ -10,7 +10,7 @@ impl<I: Iterator<Item = u32>> BytesTransferExt for I {
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fn bytes_transfer(self) -> BytesTransfer<Self> {
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fn bytes_transfer(self) -> BytesTransfer<Self> {
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BytesTransfer {
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BytesTransfer {
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iter: self,
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iter: self,
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shift: 32,
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shift: 0,
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word: 0,
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word: 0,
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}
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}
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}
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}
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@ -26,15 +26,15 @@ impl<I: Iterator<Item = u32> + Sized> Iterator for BytesTransfer<I> {
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type Item = u8;
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type Item = u8;
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fn next(&mut self) -> Option<u8> {
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fn next(&mut self) -> Option<u8> {
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if self.shift < 24 {
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if self.shift > 0 {
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self.shift += 8;
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self.shift -= 8;
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Some((self.word >> self.shift) as u8)
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Some((self.word >> self.shift) as u8)
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} else {
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} else {
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self.shift = 0;
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self.iter.next()
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self.iter.next()
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.map(|word| {
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.and_then(|word| {
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self.shift = 32;
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self.word = word;
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self.word = word;
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word as u8
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self.next()
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})
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})
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}
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}
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}
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}
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@ -272,6 +272,7 @@ impl Flash<()> {
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self.regs.config.modify(|_, w| w
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self.regs.config.modify(|_, w| w
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.man_start_en(true)
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.man_start_en(true)
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.manual_cs(true)
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.manual_cs(true)
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.endian(true)
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);
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);
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self.regs.lqspi_cfg.write(regs::LqspiCfg::zeroed()
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self.regs.lqspi_cfg.write(regs::LqspiCfg::zeroed()
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