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zynq-rs
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uart: extend regs

This commit is contained in:
Astro 2019-05-22 01:42:24 +02:00
parent b296fc1d7f
commit 673d585d2f
1 changed files with 16 additions and 4 deletions
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14
src/uart/regs.rs
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@ -14,9 +14,14 @@ pub enum ParityMode {
OddParity = 0b001, OddParity = 0b001,
ForceTo0 = 0b010, ForceTo0 = 0b010,
ForceTo1 = 0b011, ForceTo1 = 0b011,
None = 0b111, None = 0b100,
} }
pub enum StopBits {
One = 0b00,
OneAndHalf = 0b01,
Two = 0b10,
}
#[repr(C)] #[repr(C)]
pub struct RegisterBlock { pub struct RegisterBlock {
@ -56,7 +61,14 @@ register_bit!(control, stpbrk, 8);
register!(mode, Mode, RW, u32); register!(mode, Mode, RW, u32);
/// Channel mode: Defines the mode of operation of the UART. /// Channel mode: Defines the mode of operation of the UART.
register_bits!(mode, chmode, u8, 8, 9); register_bits!(mode, chmode, u8, 8, 9);
/// Number of stop bits
register_bits!(mode, nbstop, u8, 6, 7);
/// Parity type select
register_bits!(mode, par, u8, 3, 5); register_bits!(mode, par, u8, 3, 5);
/// Character length select
register_bits!(mode, chrl, u8, 1, 2);
/// Clock source select
register_bit!(mode, clks, 0);
register!(baud_rate_gen, BaudRateGen, RW, u32); register!(baud_rate_gen, BaudRateGen, RW, u32);
register_bits!(baud_rate_gen, cd, u16, 0, 15); register_bits!(baud_rate_gen, cd, u16, 0, 15);