mlabs-kb-cobalt/posts/000001.md

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000001 - What is the clocking for each ARTIQ controller?	article.liquid	sinara clocking kasli metlino sayma kc705 zc706	true

Article #000001

What is the clocking for each ARTIQ controller?

	Internal clock source	→RTIO freq	External clock source	→RTIO freq
Kasli Standalone/Master	Oscillator at Si5324 @ 114.285MHz ⁽³⁾	125MHz	Front panel SMA @ {10MHz, 100MHz, 125MHz} ⁽⁴⁾⁽⁶⁾	125MHz ⁽⁷⁾
Kasli Satellite	No uplink: Oscillator at FPGA @ 125MHz ⁽⁵⁾	125MHz	Has uplink: Clock recovered from uplink @ 125MHz ⁽⁵⁾	125MHz
Metlino Master	Oscillator at Si5324 @ 114.285MHz ⁽³⁾	150MHz	Currently not supported	--
Sayma Satellite	No uplink: Oscillator at FPGA @ 50MHz ⁽⁵⁾	150MHz	Has uplink: Clock recovered from uplink @ 150MHz ⁽⁵⁾	150MHz
KC705 Standalone	Oscillator at FPGA @ 200MHz	125MHz	User SMA clock (J11,J12) @ 125MHz	125MHz
ZC706 Standalone (WIP)	Oscillator at FPGA (PS clock) @ 33.3MHz ⁽⁸⁾	125MHz	User SMA clock (J67,J68) @ 125MHz	125MHz

Notes:

1. All possible combinations of supported clock frequencies are defined in the firmware.
2. For all controllers, the source clock signal always passes through several clock buffers. The table above only reflects the starting point, while the actual clock distribution system is more involved.
3. For standalone or master variants that use Si5324 for clock synthesis, if the firmware is configured to operate without external clocking, the RTIO clock is generated from the crystal connected to Si5324 (at pins XA/XB). Si5324 would enter "Free Run" mode (see Section 6.5 of Si53xx Reference Manual) to select the crystal as the input clock in place of CLKIN2.
4. For standalone or master variants that use Si5324 for clock synthesis, the conversion from the external clock to the RTIO clock involves the use of Si5324's internal PLL. This introduces two major non-deterministic side effects to external clocking on these systems:
   • There is additional phase noise at certain frequencies during the conversion (consult Section 3.3 of Si5324 datasheet).
   • On each reboot, the internal PLL needs to perform an internal self-calibration (ICAL), which introduces an input-to-output phase skew that is uncontrolled and random per calibration (consult Section 3.3 of Si5324 datasheet).
5. For satellite variants that use Si5324 for clock distribution, the clock source is selected by the firmware at the SiPhaser logic submodule based on the uplink status. For simplicity, the table above uses "external" and "internal" to indicate the presence and absence of an established uplink respectively. The internal clock source is fed to the FPGA's internal frequency synthesizer (e.g. Xilinx's MMCM), which produces a clock at the same frequency as the target RTIO frequency for clock alignment with uplink. The fully recovered clock is then fed to Si5324's CLKIN1 while it is in "Free Run" mode, producing a jitter-attenuated RTIO clock for DRTIO transceivers.
6. In Kasli v1 and v2, there is a difference in the path connecting the external clock at the SMA connectors and the RTIO clock. In v1, the external clock is connected to Si5324's CLKIN2. In v2, the external clock goes through the FPGA's internal buffers and registers and is then forwarded to Si5324's CLKIN1.
7. In a Kasli standalone or master variant, the RTIO clock must operate at 125 MHz. If the external clock is at 125 MHz, the firmware allows the user to bypass Si5324's internal PLL, and directly feed the external clock to the output buffers. The output RTIO clock signal will generally have reduced phase noise comparing with the output synthesized without bypassing. If the external clock is not equal to 125 MHz, it cannot be used to bypass Si5324 to create the RTIO clock.
   • Note that toggling on and off the bypass mode is done with a configuration key rtio_clock in the storage area of the flash memory. This key cannot be used to determine whether or not the firmware can operate without external clocking. See the subsection in #000002 for details about setting rtio_clock.
8. In a ZC705 standalone variant, clock generation is done by the PS (Processing System) of the Zynq-7000 SoC, which takes the on-board 33.3 MHz oscillator as the source (PS_CLK) and gives FCLKs (frequency-programmable clocks) to the PL (Programmable Logic, belonging to 7 series FPGA family). The RTIO frequency is generated within the PL.