forked from M-Labs/zynq-rs
zynq::ddr: only enable_ddr if no clock yet
that's only an issue for the cora z7
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@ -36,8 +36,11 @@ impl DdrRam {
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/// 10.6.1 DDR Clock Initialization
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fn clock_setup() -> CpuClocks {
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let clocks = CpuClocks::get();
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CpuClocks::enable_ddr(clocks.arm);
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if clocks.ddr == 0 {
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CpuClocks::enable_ddr(clocks.arm);
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}
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let clocks = CpuClocks::get();
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println!("Clocks: {:?}", clocks);
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let ddr3x_clk_divisor = ((clocks.ddr - 1) / DDR_FREQ + 1).min(255) as u8;
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let ddr2x_clk_divisor = 3 * ddr3x_clk_divisor / 2;
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