forked from M-Labs/zynq-rs
zynq::ddr: don't overwrite slcr.ddr_pll_ctrl
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637bb35f43
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f199ac68b4
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@ -42,10 +42,6 @@ impl DdrRam {
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let ddr2x_clk_divisor = 3 * ddr3x_clk_divisor / 2;
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.ddr_pll_ctrl.write(
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slcr::PllCtrl::zeroed()
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);
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slcr.ddr_clk_ctrl.write(
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slcr::DdrClkCtrl::zeroed()
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.ddr_2xclkact(true)
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