forked from M-Labs/zynq-rs
zynq::flash: add more initialization
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7107244a6e
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@ -160,6 +160,9 @@ impl Flash<()> {
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}
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fn configure(&mut self, divider: u32) {
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self.disable_interrupts();
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self.clear_rx_fifo();
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// for a baud_rate_div=1 LPBK_DLY_ADJ would be required
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let mut baud_rate_div = 2u32;
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while baud_rate_div < 7 && 2u32.pow(1 + baud_rate_div) < divider {
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@ -170,8 +173,33 @@ impl Flash<()> {
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.baud_rate_div(baud_rate_div as u8)
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.mode_sel(true)
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.leg_flsh(true)
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// 32 bits TX FIFO width
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.fifo_width(0b11)
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);
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// Initialize RX/TX pipes thresholds
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unsafe {
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self.regs.rx_thres.write(32);
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self.regs.tx_thres.write(1);
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}
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}
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fn disable_interrupts(&mut self) {
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self.regs.intr_dis.write(
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regs::IntrDis::zeroed()
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.rx_overflow(true)
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.tx_fifo_not_full(true)
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.tx_fifo_full(true)
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.rx_fifo_not_empty(true)
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.rx_fifo_full(true)
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.tx_fifo_underflow(true)
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);
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}
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fn clear_rx_fifo(&self) {
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while self.regs.intr_status.read().rx_fifo_not_empty() {
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let _ = self.regs.rx_data.read();
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}
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}
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pub fn linear_addressing_mode(self) -> Flash<LinearAddressing> {
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@ -6,8 +6,8 @@ use crate::{register, register_bit, register_bits};
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pub struct RegisterBlock {
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pub config: Config,
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pub intr_status: IntrStatus,
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pub intr_en: RW<u32>,
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pub intr_dis: RW<u32>,
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pub intr_en: IntrEn,
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pub intr_dis: IntrDis,
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pub intr_mask: RO<u32>,
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pub enable: Enable,
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pub delay: RW<u32>,
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@ -85,6 +85,22 @@ register_bit!(intr_status, rx_fifo_not_empty, 4);
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register_bit!(intr_status, rx_fifo_full, 5);
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register_bit!(intr_status, tx_fifo_underflow, 6);
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register!(intr_en, IntrEn, WO, u32);
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register_bit!(intr_en, rx_overflow, 0);
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register_bit!(intr_en, tx_fifo_not_full, 2);
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register_bit!(intr_en, tx_fifo_full, 3);
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register_bit!(intr_en, rx_fifo_not_empty, 4);
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register_bit!(intr_en, rx_fifo_full, 5);
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register_bit!(intr_en, tx_fifo_underflow, 6);
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register!(intr_dis, IntrDis, WO, u32);
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register_bit!(intr_dis, rx_overflow, 0);
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register_bit!(intr_dis, tx_fifo_not_full, 2);
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register_bit!(intr_dis, tx_fifo_full, 3);
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register_bit!(intr_dis, rx_fifo_not_empty, 4);
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register_bit!(intr_dis, rx_fifo_full, 5);
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register_bit!(intr_dis, tx_fifo_underflow, 6);
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register!(enable, Enable, RW, u32);
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register_bit!(enable, spi_en, 0);
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