fsagbuya/zynq-rs
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compile fixes

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Astro 2019-07-01 00:15:17 +02:00
parent 5a8d714627
commit b9c233b05b
2 changed files with 2 additions and 1 deletions
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1
src/eth/mod.rs
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@ -1,5 +1,6 @@
use crate::regs::*; use crate::regs::*;
use crate::slcr; use crate::slcr;
use crate::println;
pub mod phy; pub mod phy;
mod regs; mod regs;

2
src/eth/tx.rs
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@ -1,5 +1,6 @@
use core::ops::{Deref, DerefMut}; use core::ops::{Deref, DerefMut};
use crate::{register, register_bit, register_bits, register_bits_typed, regs::*}; use crate::{register, register_bit, register_bits, register_bits_typed, regs::*};
use crate::println;
use super::{MTU, regs}; use super::{MTU, regs};
/// Descriptor entry /// Descriptor entry
@ -52,7 +53,6 @@ impl<'a> DescList<'a> {
// every frame contains 1 packet // every frame contains 1 packet
.last_buffer(true) .last_buffer(true)
); );
);
} }
DescList { DescList {