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libboard_zynq::slcr: fix arm_clk_ctrl srcsel, doc

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Astro 2020-01-23 00:28:47 +01:00
parent d88ba97a03
commit 99a2e5d621
1 changed files with 4 additions and 2 deletions
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libboard_zynq/src/slcr.rs
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@ -330,8 +330,10 @@ register_bit!(arm_clk_ctrl, cpu_1xclkact, 27);
register_bit!(arm_clk_ctrl, cpu_2xclkact, 26);
register_bit!(arm_clk_ctrl, cpu_3or2xclkact, 25);
register_bit!(arm_clk_ctrl, cpu_6or4xclkact, 24);
register_bits!(arm_clk_ctrl, divisor, u8, 8, 13);
register_bits_typed!(arm_clk_ctrl, srcsel, u8, ArmPllSource, 8, 13);
register_bits!(arm_clk_ctrl,
/// should be divisible by 2 (see TRM: 25.2 CPU Clock)
divisor, u8, 8, 13);
register_bits_typed!(arm_clk_ctrl, srcsel, u8, ArmPllSource, 4, 5);
register!(ddr_clk_ctrl, DdrClkCtrl, RW, u32);
register_bit!(ddr_clk_ctrl, ddr_3xclkact, 0);