fsagbuya
/
zynq-rs
forked from M-Labs/zynq-rs
1
0
Fork 0
Code Pull Requests Activity

zynq: replace unnecessary slcr::unlocked with new

This commit is contained in:
Astro 2019-10-31 20:47:05 +01:00
parent 54e4b9281f
commit 6bee1f44f4
4 changed files with 309 additions and 320 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
src/zynq/clocks.rs
View File

@ -99,30 +99,29 @@ impl CpuClocks {
.nth(0)
.expect("PLL_FDIV_LOCK_PARAM")
.1.clone();
slcr::RegisterBlock::unlocked(|regs| {
regs.ddr_pll_ctrl.modify(|_, w| w
let slcr = slcr::RegisterBlock::new();
slcr.ddr_pll_ctrl.modify(|_, w| w
.pll_pwrdwn(false)
.pll_bypass_force(true)
.pll_fdiv(fdiv)
);
regs.ddr_pll_cfg.write(
slcr.ddr_pll_cfg.write(
slcr::PllCfg::zeroed()
.pll_res(pll_res)
.pll_cp(pll_cp)
.lock_cnt(lock_cnt)
);
regs.ddr_pll_ctrl.modify(|_, w| w
slcr.ddr_pll_ctrl.modify(|_, w| w
.pll_reset(true)
);
regs.ddr_pll_ctrl.modify(|_, w| w
slcr.ddr_pll_ctrl.modify(|_, w| w
.pll_reset(false)
);
while ! regs.pll_status.read().ddr_pll_lock() {}
regs.ddr_pll_ctrl.modify(|_, w| w
while ! slcr.pll_status.read().ddr_pll_lock() {}
slcr.ddr_pll_ctrl.modify(|_, w| w
.pll_bypass_force(false)
.pll_bypass_qual(false)
);
});
}
}

9
src/zynq/ddr/mod.rs
View File

@ -42,7 +42,7 @@ impl DdrRam {
let ddr3x_clk_divisor = ((clocks.ddr - 1) / DDR_FREQ + 1).min(255) as u8;
let ddr2x_clk_divisor = 3 * ddr3x_clk_divisor / 2;
slcr::RegisterBlock::unlocked(|slcr| {
let slcr = slcr::RegisterBlock::new();
slcr.ddr_clk_ctrl.write(
slcr::DdrClkCtrl::zeroed()
.ddr_2xclkact(true)
@ -50,7 +50,6 @@ impl DdrRam {
.ddr_2xclk_divisor(ddr2x_clk_divisor)
.ddr_3xclk_divisor(ddr3x_clk_divisor)
);
});
clocks
}
@ -62,7 +61,7 @@ impl DdrRam {
let divisor1 = 1 + (clocks.ddr / DCI_FREQ / u32::from(divisor0))
.max(1).min(63) as u8;
slcr::RegisterBlock::unlocked(|slcr| {
let slcr = slcr::RegisterBlock::new();
// Step 1.
slcr.dci_clk_ctrl.write(
slcr::DciClkCtrl::zeroed()
@ -96,13 +95,12 @@ impl DdrRam {
);
// Step 2.e.
while ! slcr.ddriob_dci_status.read().done() {}
});
}
/// Zynq-7000 AP SoC Technical Reference Manual:
/// 10.6.3 DDR IOB Configuration
fn configure_iob() {
slcr::RegisterBlock::unlocked(|slcr| {
let slcr = slcr::RegisterBlock::new();
let addr_config = slcr::DdriobConfig::zeroed()
.output_en(slcr::DdriobOutputEn::Obuf);
slcr.ddriob_addr0.write(addr_config.clone());
@ -156,7 +154,6 @@ impl DdrRam {
.vref_sel(vref_sel)
.vref_int_en(false)
);
});
}
/// Reset DDR controller

9
src/zynq/eth/mod.rs
View File

@ -25,7 +25,7 @@ pub struct Eth<'r, RX, TX> {
impl<'r> Eth<'r, (), ()> {
pub fn default(macaddr: [u8; 6]) -> Self {
slcr::RegisterBlock::unlocked(|slcr| {
let slcr = slcr::RegisterBlock::new();
// Manual example: 0x0000_1280
// MDIO
slcr.mio_pin_53.write(
@ -150,7 +150,6 @@ impl<'r> Eth<'r, (), ()> {
slcr::GpiobCtrl::zeroed()
.vref_en(true)
);
});
Self::gem0(macaddr)
}
@ -196,7 +195,7 @@ impl<'r, RX, TX> Eth<'r, RX, TX> {
let d0 = (io_pll / tx_clock).min(63);
let d1 = (io_pll / tx_clock / d0).min(63);
slcr::RegisterBlock::unlocked(|slcr| {
let slcr = slcr::RegisterBlock::new();
slcr.gem0_clk_ctrl.write(
// 0x0050_0801: 8, 5: 100 Mb/s
// ...: 8, 1: 1000 Mb/s
@ -212,7 +211,6 @@ impl<'r, RX, TX> Eth<'r, RX, TX> {
slcr::RclkCtrl::zeroed()
.clkact(true)
);
});
}
pub fn setup_gem1_clock(tx_clock: u32) {
@ -220,7 +218,7 @@ impl<'r, RX, TX> Eth<'r, RX, TX> {
let d0 = (io_pll / tx_clock).min(63);
let d1 = (io_pll / tx_clock / d0).min(63);
slcr::RegisterBlock::unlocked(|slcr| {
let slcr = slcr::RegisterBlock::new();
slcr.gem1_clk_ctrl.write(
slcr::GemClkCtrl::zeroed()
.clkact(true)
@ -234,7 +232,6 @@ impl<'r, RX, TX> Eth<'r, RX, TX> {
slcr::RclkCtrl::zeroed()
.clkact(true)
);
});
}
pub fn start_rx<'rx>(self, rx_list: &'rx mut [rx::DescEntry], rx_buffers: &'rx mut [[u8; MTU]]) -> Eth<'r, rx::DescList<'rx>, TX> {

12
src/zynq/uart/mod.rs
View File

@ -14,7 +14,7 @@ pub struct Uart {
impl Uart {
#[cfg(feature = "target_zc706")]
pub fn serial(baudrate: u32) -> Self {
slcr::RegisterBlock::unlocked(|slcr| {
let slcr = slcr::RegisterBlock::new();
// Route UART 1 RxD/TxD Signals to MIO Pins
// TX pin
slcr.mio_pin_48.write(
@ -31,13 +31,12 @@ impl Uart {
.io_type(slcr::IoBufferType::Lvcmos18)
.pullup(true)
);
});
Self::uart1(baudrate)
}
#[cfg(feature = "target_cora_z7_10")]
pub fn serial(baudrate: u32) -> Self {
slcr::RegisterBlock::unlocked(|slcr| {
let slcr = slcr::RegisterBlock::new();
// Route UART 0 RxD/TxD Signals to MIO Pins
// TX pin
slcr.mio_pin_15.write(
@ -54,16 +53,14 @@ impl Uart {
.io_type(slcr::IoBufferType::Lvcmos33)
.pullup(true)
);
});
Self::uart0(baudrate)
}
pub fn uart0(baudrate: u32) -> Self {
slcr::RegisterBlock::unlocked(|slcr| {
let slcr = slcr::RegisterBlock::new();
slcr.uart_rst_ctrl.reset_uart0();
slcr.aper_clk_ctrl.enable_uart0();
slcr.uart_clk_ctrl.enable_uart0();
});
let mut self_ = Uart {
regs: regs::RegisterBlock::uart0(),
};
@ -72,11 +69,10 @@ impl Uart {
}
pub fn uart1(baudrate: u32) -> Self {
slcr::RegisterBlock::unlocked(|slcr| {
let slcr = slcr::RegisterBlock::new();
slcr.uart_rst_ctrl.reset_uart1();
slcr.aper_clk_ctrl.enable_uart1();
slcr.uart_clk_ctrl.enable_uart1();
});
let mut self_ = Uart {
regs: regs::RegisterBlock::uart1(),
};