fsagbuya
/
zynq-rs
forked from M-Labs/zynq-rs
1
0
Fork 0
Code Pull Requests Activity

libcortex_a9: allow access for full 1GB of DDR

This commit is contained in:
Astro 2020-05-09 01:00:48 +02:00
parent 4e1f46b3e2
commit 66cd0c7630
1 changed files with 1 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
libcortex_a9/src/mmu.rs
View File

@ -123,7 +123,7 @@ impl L1Table {
bufferable: true,
});
/* (DDR cacheable) */
for ddr in 1..=0x1ff {
for ddr in 1..=0x3ff {
self.direct_mapped_section(ddr, L1Section {
global: true,
shareable: true,
@ -135,19 +135,6 @@ impl L1Table {
bufferable: false,
});
}
/* (unassigned/reserved). */
for undef in 0x1ff..=0x3ff {
self.direct_mapped_section(undef, L1Section {
global: false,
shareable: false,
access: AccessPermissions::PermissionFault,
tex: 0,
domain: 0,
exec: false,
cacheable: false,
bufferable: false,
});
}
/* 0x40000000 - 0x7fffffff (FPGA slave0) */
for fpga_slave in 0x400..=0x7ff {
self.direct_mapped_section(fpga_slave, L1Section {