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Merge pull request 'libboard_zynq: dead code, peripheral & regblock ctor names consistency' (#63) from harry/zynq-rs:cleanup into master

This commit is contained in:
Astro 2020-08-17 23:38:22 +08:00
commit 64db9b0142
22 changed files with 90 additions and 114 deletions

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@ -56,8 +56,8 @@ static CORE1_RESTART: AtomicBool = AtomicBool::new(false);
#[naked] #[naked]
pub unsafe extern "C" fn IRQ() { pub unsafe extern "C" fn IRQ() {
if MPIDR.read().cpu_id() == 1{ if MPIDR.read().cpu_id() == 1{
let mpcore = mpcore::RegisterBlock::new(); let mpcore = mpcore::RegisterBlock::mpcore();
let mut gic = gic::InterruptController::new(mpcore); let mut gic = gic::InterruptController::gic(mpcore);
let id = gic.get_interrupt_id(); let id = gic.get_interrupt_id();
if id.0 == 0 { if id.0 == 0 {
gic.end_interrupt(id); gic.end_interrupt(id);
@ -75,7 +75,7 @@ pub unsafe extern "C" fn IRQ() {
} }
pub fn restart_core1() { pub fn restart_core1() {
let mut interrupt_controller = gic::InterruptController::new(mpcore::RegisterBlock::new()); let mut interrupt_controller = gic::InterruptController::gic(mpcore::RegisterBlock::mpcore());
CORE1_RESTART.store(true, Ordering::Relaxed); CORE1_RESTART.store(true, Ordering::Relaxed);
interrupt_controller.send_sgi(gic::InterruptId(0), gic::CPUCore::Core1.into()); interrupt_controller.send_sgi(gic::InterruptId(0), gic::CPUCore::Core1.into());
while CORE1_RESTART.load(Ordering::Relaxed) { while CORE1_RESTART.load(Ordering::Relaxed) {
@ -87,7 +87,7 @@ pub fn restart_core1() {
pub fn main_core0() { pub fn main_core0() {
// zynq::clocks::CpuClocks::enable_io(1_250_000_000); // zynq::clocks::CpuClocks::enable_io(1_250_000_000);
println!("\nzc706 main"); println!("\nzc706 main");
let mut interrupt_controller = gic::InterruptController::new(mpcore::RegisterBlock::new()); let mut interrupt_controller = gic::InterruptController::gic(mpcore::RegisterBlock::mpcore());
interrupt_controller.enable_interrupts(); interrupt_controller.enable_interrupts();
// ps7_init::apply(); // ps7_init::apply();
libboard_zynq::stdio::drop_uart(); libboard_zynq::stdio::drop_uart();
@ -97,7 +97,7 @@ pub fn main_core0() {
info!( info!(
"Boot mode: {:?}", "Boot mode: {:?}",
zynq::slcr::RegisterBlock::new() zynq::slcr::RegisterBlock::slcr()
.boot_mode .boot_mode
.read() .read()
.boot_mode_pins() .boot_mode_pins()
@ -131,7 +131,7 @@ pub fn main_core0() {
clocks.cpu_1x() clocks.cpu_1x()
); );
let mut flash = zynq::flash::Flash::new(200_000_000).linear_addressing_mode(); let mut flash = zynq::flash::Flash::flash(200_000_000).linear_addressing_mode();
let flash_ram: &[u8] = unsafe { core::slice::from_raw_parts(flash.ptr(), flash.size()) }; let flash_ram: &[u8] = unsafe { core::slice::from_raw_parts(flash.ptr(), flash.size()) };
for i in 0..=1 { for i in 0..=1 {
print!("Flash {}:", i); print!("Flash {}:", i);
@ -144,7 +144,7 @@ pub fn main_core0() {
let timer = libboard_zynq::timer::GlobalTimer::start(); let timer = libboard_zynq::timer::GlobalTimer::start();
let mut ddr = zynq::ddr::DdrRam::new(); let mut ddr = zynq::ddr::DdrRam::ddrram();
#[cfg(not(feature = "target_zc706"))] #[cfg(not(feature = "target_zc706"))]
ddr.memtest(); ddr.memtest();
ram::init_alloc_ddr(&mut ddr); ram::init_alloc_ddr(&mut ddr);
@ -207,7 +207,7 @@ pub fn main_core0() {
// Test I2C // Test I2C
#[cfg(feature = "target_zc706")] #[cfg(feature = "target_zc706")]
{ {
let mut i2c = zynq::i2c::I2C::i2c(); let mut i2c = zynq::i2c::I2c::i2c0();
i2c.init(); i2c.init();
println!("I2C bit-banging enabled"); println!("I2C bit-banging enabled");
let mut eeprom = zynq::i2c::eeprom::EEPROM::new(&mut i2c, 16); let mut eeprom = zynq::i2c::eeprom::EEPROM::new(&mut i2c, 16);
@ -237,7 +237,7 @@ pub fn main_core0() {
println!(""); println!("");
} }
let eth = zynq::eth::Eth::default(HWADDR.clone()); let eth = zynq::eth::Eth::eth0(HWADDR.clone());
println!("Eth on"); println!("Eth on");
const RX_LEN: usize = 4096; const RX_LEN: usize = 4096;
@ -331,7 +331,7 @@ static DONE: Mutex<bool> = Mutex::new(false);
#[no_mangle] #[no_mangle]
pub fn main_core1() { pub fn main_core1() {
println!("Hello from core1!"); println!("Hello from core1!");
let mut interrupt_controller = gic::InterruptController::new(mpcore::RegisterBlock::new()); let mut interrupt_controller = gic::InterruptController::gic(mpcore::RegisterBlock::mpcore());
interrupt_controller.enable_interrupts(); interrupt_controller.enable_interrupts();
let req = unsafe { &mut CORE1_REQ.1 }; let req = unsafe { &mut CORE1_REQ.1 };
let res = unsafe { &mut CORE1_RES.0 }; let res = unsafe { &mut CORE1_RES.0 };

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@ -14,7 +14,7 @@ enum CpuClockMode {
impl CpuClockMode { impl CpuClockMode {
pub fn get() -> Self { pub fn get() -> Self {
let regs = slcr::RegisterBlock::new(); let regs = slcr::RegisterBlock::slcr();
if regs.clk_621_true.read().clk_621_true() { if regs.clk_621_true.read().clk_621_true() {
CpuClockMode::C621 CpuClockMode::C621
} else { } else {
@ -59,7 +59,7 @@ impl Clocks {
} }
pub fn cpu_6x4x(&self) -> u32 { pub fn cpu_6x4x(&self) -> u32 {
let slcr = slcr::RegisterBlock::new(); let slcr = slcr::RegisterBlock::slcr();
let arm_clk_ctrl = slcr.arm_clk_ctrl.read(); let arm_clk_ctrl = slcr.arm_clk_ctrl.read();
let pll = match arm_clk_ctrl.srcsel() { let pll = match arm_clk_ctrl.srcsel() {
ArmPllSource::ArmPll => self.arm, ArmPllSource::ArmPll => self.arm,
@ -92,7 +92,7 @@ impl Clocks {
} }
pub fn uart_ref_clk(&self) -> u32 { pub fn uart_ref_clk(&self) -> u32 {
let regs = slcr::RegisterBlock::new(); let regs = slcr::RegisterBlock::slcr();
let uart_clk_ctrl = regs.uart_clk_ctrl.read(); let uart_clk_ctrl = regs.uart_clk_ctrl.read();
let pll = match uart_clk_ctrl.srcsel() { let pll = match uart_clk_ctrl.srcsel() {
slcr::PllSource::ArmPll => slcr::PllSource::ArmPll =>
@ -106,7 +106,7 @@ impl Clocks {
} }
pub fn sdio_ref_clk(&self) -> u32 { pub fn sdio_ref_clk(&self) -> u32 {
let regs = slcr::RegisterBlock::new(); let regs = slcr::RegisterBlock::slcr();
let sdio_clk_ctrl = regs.sdio_clk_ctrl.read(); let sdio_clk_ctrl = regs.sdio_clk_ctrl.read();
let pll = match sdio_clk_ctrl.srcsel() { let pll = match sdio_clk_ctrl.srcsel() {
slcr::PllSource::ArmPll => slcr::PllSource::ArmPll =>

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@ -44,7 +44,7 @@ pub trait ClockSource {
/// get configured frequency /// get configured frequency
fn freq() -> u32 { fn freq() -> u32 {
let mut slcr = slcr::RegisterBlock::new(); let mut slcr = slcr::RegisterBlock::slcr();
let (pll_ctrl, _, _) = Self::pll_regs(&mut slcr); let (pll_ctrl, _, _) = Self::pll_regs(&mut slcr);
u32::from(pll_ctrl.read().pll_fdiv()) * PS_CLK u32::from(pll_ctrl.read().pll_fdiv()) * PS_CLK
} }

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@ -22,12 +22,12 @@ pub struct DdrRam {
} }
impl DdrRam { impl DdrRam {
pub fn new() -> Self { pub fn ddrram() -> Self {
let clocks = Self::clock_setup(); let clocks = Self::clock_setup();
Self::calibrate_iob_impedance(&clocks); Self::calibrate_iob_impedance(&clocks);
Self::configure_iob(); Self::configure_iob();
let regs = unsafe { regs::RegisterBlock::new() }; let regs = unsafe { regs::RegisterBlock::ddrc() };
let mut ddr = DdrRam { regs }; let mut ddr = DdrRam { regs };
ddr.configure(); ddr.configure();
ddr.reset_ddrc(); ddr.reset_ddrc();

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@ -1,6 +1,6 @@
use volatile_register::{RO, RW}; use volatile_register::{RO, RW};
use libregister::{register, register_bit, register_bits, register_bits_typed}; use libregister::{register, register_at, register_bit, register_bits, register_bits_typed};
#[allow(unused)] #[allow(unused)]
#[derive(Clone, Copy)] #[derive(Clone, Copy)]
@ -158,11 +158,7 @@ pub struct RegisterBlock {
pub lpddr_ctrl3: RW<u32>, pub lpddr_ctrl3: RW<u32>,
} }
impl RegisterBlock { register_at!(RegisterBlock, 0xF8006000, ddrc);
pub unsafe fn new() -> &'static mut Self {
&mut *(0xF8006000 as *mut _)
}
}
register!(ddrc_ctrl, DdrcCtrl, RW, u32); register!(ddrc_ctrl, DdrcCtrl, RW, u32);
register_bit!(ddrc_ctrl, register_bit!(ddrc_ctrl,

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@ -148,7 +148,7 @@ pub struct Eth<GEM: Gem, RX, TX> {
} }
impl Eth<Gem0, (), ()> { impl Eth<Gem0, (), ()> {
pub fn default(macaddr: [u8; 6]) -> Self { pub fn eth0(macaddr: [u8; 6]) -> Self {
slcr::RegisterBlock::unlocked(|slcr| { slcr::RegisterBlock::unlocked(|slcr| {
// Manual example: 0x0000_1280 // Manual example: 0x0000_1280
// MDIO // MDIO
@ -280,19 +280,22 @@ impl Eth<Gem0, (), ()> {
} }
pub fn gem0(macaddr: [u8; 6]) -> Self { pub fn gem0(macaddr: [u8; 6]) -> Self {
Self::new(macaddr) Self::gem_common(macaddr)
} }
} }
impl Eth<Gem1, (), ()> { impl Eth<Gem1, (), ()> {
// TODO: Add a `eth1()`
pub fn gem1(macaddr: [u8; 6]) -> Self { pub fn gem1(macaddr: [u8; 6]) -> Self {
Self::new(macaddr) Self::gem_common(macaddr)
} }
} }
impl<GEM: Gem> Eth<GEM, (), ()> { impl<GEM: Gem> Eth<GEM, (), ()> {
fn new(macaddr: [u8; 6]) -> Self { fn gem_common(macaddr: [u8; 6]) -> Self {
GEM::setup_clock(TX_1000); GEM::setup_clock(TX_1000);
let mut inner = EthInner { let mut inner = EthInner {

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@ -1,6 +1,6 @@
use volatile_register::{RO, WO, RW}; use volatile_register::{RO, WO, RW};
use libregister::{register, register_bit, register_bits, register_bits_typed}; use libregister::{register, register_at, register_bit, register_bits, register_bits_typed};
#[repr(C)] #[repr(C)]
pub struct RegisterBlock { pub struct RegisterBlock {
@ -110,18 +110,8 @@ pub struct RegisterBlock {
pub design_cfg5: RO<u32>, pub design_cfg5: RO<u32>,
} }
impl RegisterBlock { register_at!(RegisterBlock, 0xE000B000, gem0);
const GEM0: *mut Self = 0xE000B000 as *mut _; register_at!(RegisterBlock, 0xE000C000, gem1);
const GEM1: *mut Self = 0xE000C000 as *mut _;
pub fn gem0() -> &'static mut Self {
unsafe { &mut *Self::GEM0 }
}
pub fn gem1() -> &'static mut Self {
unsafe { &mut *Self::GEM1 }
}
}
register!(net_ctrl, NetCtrl, RW, u32); register!(net_ctrl, NetCtrl, RW, u32);
register_bit!(net_ctrl, loopback_local, 1); register_bit!(net_ctrl, loopback_local, 1);

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@ -116,7 +116,7 @@ impl<MODE> Flash<MODE> {
} }
impl Flash<()> { impl Flash<()> {
pub fn new(clock: u32) -> Self { pub fn flash(clock: u32) -> Self {
Self::enable_clocks(clock); Self::enable_clocks(clock);
Self::setup_signals(); Self::setup_signals();
Self::reset(); Self::reset();

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@ -1,6 +1,6 @@
use volatile_register::{RO, WO, RW}; use volatile_register::{RO, WO, RW};
use libregister::{register, register_bit, register_bits}; use libregister::{register, register_at, register_bit, register_bits};
#[repr(C)] #[repr(C)]
pub struct RegisterBlock { pub struct RegisterBlock {
@ -30,13 +30,9 @@ pub struct RegisterBlock {
pub mod_id: RW<u32>, pub mod_id: RW<u32>,
} }
impl RegisterBlock { const BASE_ADDRESS: u32 = 0xE000D000;
const BASE_ADDRESS: *mut Self = 0xE000D000 as *mut _;
pub fn qspi() -> &'static mut Self { register_at!(RegisterBlock, 0xE000D000, qspi);
unsafe { &mut *Self::BASE_ADDRESS }
}
}
register!(config, Config, RW, u32); register!(config, Config, RW, u32);
register_bit!(config, register_bit!(config,

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@ -62,7 +62,7 @@ pub struct InterruptController {
} }
impl InterruptController { impl InterruptController {
pub fn new(mpcore: &'static mut mpcore::RegisterBlock) -> Self { pub fn gic(mpcore: &'static mut mpcore::RegisterBlock) -> Self {
InterruptController { mpcore } InterruptController { mpcore }
} }

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@ -1,9 +1,9 @@
use super::I2C; use super::I2c;
use crate::time::Milliseconds; use crate::time::Milliseconds;
use embedded_hal::timer::CountDown; use embedded_hal::timer::CountDown;
pub struct EEPROM<'a> { pub struct EEPROM<'a> {
i2c: &'a mut I2C, i2c: &'a mut I2c,
port: u8, port: u8,
address: u8, address: u8,
page_size: u8, page_size: u8,
@ -12,7 +12,7 @@ pub struct EEPROM<'a> {
impl<'a> EEPROM<'a> { impl<'a> EEPROM<'a> {
#[cfg(feature = "target_zc706")] #[cfg(feature = "target_zc706")]
pub fn new(i2c: &'a mut I2C, page_size: u8) -> Self { pub fn new(i2c: &'a mut I2c, page_size: u8) -> Self {
EEPROM { EEPROM {
i2c: i2c, i2c: i2c,
port: 2, port: 2,

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@ -2,22 +2,19 @@
mod regs; mod regs;
pub mod eeprom; pub mod eeprom;
use super::clocks::Clocks;
use super::slcr; use super::slcr;
use super::time::Microseconds; use super::time::Microseconds;
use embedded_hal::timer::CountDown; use embedded_hal::timer::CountDown;
use libregister::{RegisterR, RegisterRW, RegisterW}; use libregister::{RegisterR, RegisterRW, RegisterW};
const INVALID_BUS: &'static str = "Invalid I2C bus"; pub struct I2c {
regs: regs::RegisterBlock,
pub struct I2C {
regs: regs::RegisterWrapper,
count_down: super::timer::global::CountDown<Microseconds> count_down: super::timer::global::CountDown<Microseconds>
} }
impl I2C { impl I2c {
#[cfg(feature = "target_zc706")] #[cfg(feature = "target_zc706")]
pub fn i2c() -> Self { pub fn i2c0() -> Self {
// Route I2C 0 SCL / SDA Signals to MIO Pins 50 / 51 // Route I2C 0 SCL / SDA Signals to MIO Pins 50 / 51
slcr::RegisterBlock::unlocked(|slcr| { slcr::RegisterBlock::unlocked(|slcr| {
// SCL // SCL
@ -40,14 +37,13 @@ impl I2C {
slcr.gpio_rst_ctrl.reset_gpio(); slcr.gpio_rst_ctrl.reset_gpio();
}); });
Self::ctor_common(0xFFFF - 0x000C) Self::i2c_common(0xFFFF - 0x000C)
} }
fn ctor_common(gpio_output_mask: u16) -> Self { fn i2c_common(gpio_output_mask: u16) -> Self {
// Setup register block // Setup register block
let clocks = Clocks::get();
let self_ = Self { let self_ = Self {
regs: regs::RegisterWrapper::new(), regs: regs::RegisterBlock::i2c(),
count_down: unsafe { super::timer::GlobalTimer::get() }.countdown() count_down: unsafe { super::timer::GlobalTimer::get() }.countdown()
}; };

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@ -1,5 +1,3 @@
use volatile_register::{RO, WO, RW};
use libregister::{ use libregister::{
register, register_at, register, register_at,
register_bit, register_bits register_bit, register_bits
@ -23,15 +21,15 @@ use libregister::{
// Current compatibility: // Current compatibility:
// zc706: GPIO 50, 51 == SCL, SDA // zc706: GPIO 50, 51 == SCL, SDA
pub struct RegisterWrapper { pub struct RegisterBlock {
pub gpio_output_mask: &'static mut GPIOOutputMask, pub gpio_output_mask: &'static mut GPIOOutputMask,
pub gpio_input: &'static mut GPIOInput, pub gpio_input: &'static mut GPIOInput,
pub gpio_direction: &'static mut GPIODirection, pub gpio_direction: &'static mut GPIODirection,
pub gpio_output_enable: &'static mut GPIOOutputEnable, pub gpio_output_enable: &'static mut GPIOOutputEnable,
} }
impl RegisterWrapper { impl RegisterBlock {
pub fn new() -> Self { pub fn i2c() -> Self {
Self { Self {
gpio_output_mask: GPIOOutputMask::new(), gpio_output_mask: GPIOOutputMask::new(),
gpio_input: GPIOInput::new(), gpio_input: GPIOInput::new(),

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@ -138,7 +138,7 @@ pub struct RegisterBlock {
pub icdsgir: ICDSGIR, pub icdsgir: ICDSGIR,
} }
register_at!(RegisterBlock, 0xF8F00000, new); register_at!(RegisterBlock, 0xF8F00000, mpcore);
register!(value_register, ValueRegister, RW, u32); register!(value_register, ValueRegister, RW, u32);
register_bits!(value_register, value, u32, 0, 31); register_bits!(value_register, value, u32, 0, 31);

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@ -1,6 +1,6 @@
/// ADMA library /// ADMA library
use core::mem::MaybeUninit; use core::mem::MaybeUninit;
use super::SDIO; use super::Sdio;
use libcortex_a9::cache; use libcortex_a9::cache;
use libregister::{ use libregister::{
register, register_bit, register, register_bit,
@ -32,7 +32,7 @@ impl Adma2DescTable {
} }
/// Initialize the table and setup `adma_system_address` /// Initialize the table and setup `adma_system_address`
pub fn setup(&mut self, sdio: &mut SDIO, blk_cnt: u32, buffer: &[u8]) { pub fn setup(&mut self, sdio: &mut Sdio, blk_cnt: u32, buffer: &[u8]) {
let descr_table = &mut self.0; let descr_table = &mut self.0;
let blk_size = sdio let blk_size = sdio
.regs .regs

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@ -12,7 +12,7 @@ use log::{trace, debug};
use nb; use nb;
/// Basic SDIO Struct with common low-level functions. /// Basic SDIO Struct with common low-level functions.
pub struct SDIO { pub struct Sdio {
regs: &'static mut regs::RegisterBlock, regs: &'static mut regs::RegisterBlock,
count_down: super::timer::global::CountDown<Milliseconds>, count_down: super::timer::global::CountDown<Milliseconds>,
input_clk_hz: u32, input_clk_hz: u32,
@ -48,7 +48,7 @@ pub enum CardType {
CardMmc, CardMmc,
} }
impl SDIO { impl Sdio {
/// Initialize SDIO0 /// Initialize SDIO0
/// card_detect means if we would use the card detect pin, /// card_detect means if we would use the card detect pin,
/// false to disable card detection (assume there is card inserted) /// false to disable card detection (assume there is card inserted)
@ -121,7 +121,7 @@ impl SDIO {
slcr.sdio_clk_ctrl.enable_sdio0(); slcr.sdio_clk_ctrl.enable_sdio0();
}); });
let clocks = Clocks::get(); let clocks = Clocks::get();
let mut self_ = SDIO { let mut self_ = Sdio {
regs: regs::RegisterBlock::sdio0(), regs: regs::RegisterBlock::sdio0(),
count_down: unsafe { super::timer::GlobalTimer::get() }.countdown(), count_down: unsafe { super::timer::GlobalTimer::get() }.countdown(),
input_clk_hz: clocks.sdio_ref_clk(), input_clk_hz: clocks.sdio_ref_clk(),

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@ -1,4 +1,4 @@
use super::{adma::Adma2DescTable, cmd, CardType, CmdTransferError, SDIO}; use super::{adma::Adma2DescTable, cmd, CardType, CmdTransferError, Sdio};
use libcortex_a9::cache; use libcortex_a9::cache;
use libregister::{RegisterR, RegisterRW, RegisterW}; use libregister::{RegisterR, RegisterRW, RegisterW};
use log::{trace, debug}; use log::{trace, debug};
@ -37,7 +37,7 @@ enum CardVersion {
} }
pub struct SdCard { pub struct SdCard {
sdio: SDIO, sdio: Sdio,
adma2_desc_table: Adma2DescTable, adma2_desc_table: Adma2DescTable,
card_version: CardVersion, card_version: CardVersion,
hcs: bool, hcs: bool,
@ -171,8 +171,8 @@ impl SdCard {
Ok(()) Ok(())
} }
/// Convert SDIO into SdCard struct, error if no card inserted or it is not an SD card. /// Convert Sdio into SdCard struct, error if no card inserted or it is not an SD card.
pub fn from_sdio(mut sdio: SDIO) -> Result<Self, CardInitializationError> { pub fn from_sdio(mut sdio: Sdio) -> Result<Self, CardInitializationError> {
match sdio.identify_card()? { match sdio.identify_card()? {
CardType::CardSd => (), CardType::CardSd => (),
_ => return Err(CardInitializationError::NoCardInserted), _ => return Err(CardInitializationError::NoCardInserted),
@ -192,8 +192,8 @@ impl SdCard {
Ok(_self) Ok(_self)
} }
/// Convert SdCard struct back to SDIO struct. /// Convert SdCard struct back to Sdio struct.
pub fn to_sdio(self) -> SDIO { pub fn to_sdio(self) -> Sdio {
self.sdio self.sdio
} }

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@ -253,12 +253,12 @@ pub struct RegisterBlock {
pub ddriob_dci_ctrl: DdriobDciCtrl, pub ddriob_dci_ctrl: DdriobDciCtrl,
pub ddriob_dci_status: DdriobDciStatus, pub ddriob_dci_status: DdriobDciStatus,
} }
register_at!(RegisterBlock, 0xF8000000, new); register_at!(RegisterBlock, 0xF8000000, slcr);
impl RegisterBlock { impl RegisterBlock {
/// Required to modify any sclr register /// Required to modify any sclr register
pub fn unlocked<F: FnMut(&mut Self) -> R, R>(mut f: F) -> R { pub fn unlocked<F: FnMut(&mut Self) -> R, R>(mut f: F) -> R {
let mut self_ = Self::new(); let mut self_ = Self::slcr();
self_.slcr_unlock.unlock(); self_.slcr_unlock.unlock();
let r = f(&mut self_); let r = f(&mut self_);
self_.slcr_lock.lock(); self_.slcr_lock.lock();

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@ -37,7 +37,10 @@ impl DerefMut for LazyUart {
fn deref_mut(&mut self) -> &mut Uart { fn deref_mut(&mut self) -> &mut Uart {
match self { match self {
LazyUart::Uninitialized => { LazyUart::Uninitialized => {
let uart = Uart::serial(UART_RATE); #[cfg(feature = "target_cora_z7_10")]
let uart = Uart::uart0(UART_RATE);
#[cfg(feature = "target_zc706")]
let uart = Uart::uart1(UART_RATE);
*self = LazyUart::Initialized(uart); *self = LazyUart::Initialized(uart);
self self
} }

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@ -16,13 +16,13 @@ pub struct GlobalTimer {
impl GlobalTimer { impl GlobalTimer {
/// Get the potentially uninitialized timer /// Get the potentially uninitialized timer
pub unsafe fn get() -> GlobalTimer { pub unsafe fn get() -> GlobalTimer {
let regs = mpcore::RegisterBlock::new(); let regs = mpcore::RegisterBlock::mpcore();
GlobalTimer { regs } GlobalTimer { regs }
} }
/// Get the timer with a reset /// Get the timer with a reset
pub fn start() -> GlobalTimer { pub fn start() -> GlobalTimer {
let mut regs = mpcore::RegisterBlock::new(); let mut regs = mpcore::RegisterBlock::mpcore();
Self::reset(&mut regs); Self::reset(&mut regs);
GlobalTimer { regs } GlobalTimer { regs }
} }

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@ -13,31 +13,8 @@ pub struct Uart {
} }
impl Uart { impl Uart {
#[cfg(feature = "target_zc706")]
pub fn serial(baudrate: u32) -> Self {
slcr::RegisterBlock::unlocked(|slcr| {
// Route UART 1 RxD/TxD Signals to MIO Pins
// TX pin
slcr.mio_pin_48.write(
slcr::MioPin48::zeroed()
.l3_sel(0b111)
.io_type(slcr::IoBufferType::Lvcmos18)
.pullup(true)
);
// RX pin
slcr.mio_pin_49.write(
slcr::MioPin49::zeroed()
.tri_enable(true)
.l3_sel(0b111)
.io_type(slcr::IoBufferType::Lvcmos18)
.pullup(true)
);
});
Self::uart1(baudrate)
}
#[cfg(feature = "target_cora_z7_10")] #[cfg(feature = "target_cora_z7_10")]
pub fn serial(baudrate: u32) -> Self { pub fn uart0(baudrate: u32) -> Self {
slcr::RegisterBlock::unlocked(|slcr| { slcr::RegisterBlock::unlocked(|slcr| {
// Route UART 0 RxD/TxD Signals to MIO Pins // Route UART 0 RxD/TxD Signals to MIO Pins
// TX pin // TX pin
@ -56,10 +33,7 @@ impl Uart {
.pullup(true) .pullup(true)
); );
}); });
Self::uart0(baudrate)
}
pub fn uart0(baudrate: u32) -> Self {
slcr::RegisterBlock::unlocked(|slcr| { slcr::RegisterBlock::unlocked(|slcr| {
slcr.uart_rst_ctrl.reset_uart0(); slcr.uart_rst_ctrl.reset_uart0();
slcr.aper_clk_ctrl.enable_uart0(); slcr.aper_clk_ctrl.enable_uart0();
@ -72,7 +46,27 @@ impl Uart {
self_ self_
} }
#[cfg(feature = "target_zc706")]
pub fn uart1(baudrate: u32) -> Self { pub fn uart1(baudrate: u32) -> Self {
slcr::RegisterBlock::unlocked(|slcr| {
// Route UART 1 RxD/TxD Signals to MIO Pins
// TX pin
slcr.mio_pin_48.write(
slcr::MioPin48::zeroed()
.l3_sel(0b111)
.io_type(slcr::IoBufferType::Lvcmos18)
.pullup(true)
);
// RX pin
slcr.mio_pin_49.write(
slcr::MioPin49::zeroed()
.tri_enable(true)
.l3_sel(0b111)
.io_type(slcr::IoBufferType::Lvcmos18)
.pullup(true)
);
});
slcr::RegisterBlock::unlocked(|slcr| { slcr::RegisterBlock::unlocked(|slcr| {
slcr.uart_rst_ctrl.reset_uart1(); slcr.uart_rst_ctrl.reset_uart1();
slcr.aper_clk_ctrl.enable_uart1(); slcr.aper_clk_ctrl.enable_uart1();

View File

@ -43,7 +43,7 @@ pub unsafe extern "C" fn Reset() -> ! {
unsafe fn boot_core0() -> ! { unsafe fn boot_core0() -> ! {
l1_cache_init(); l1_cache_init();
let mpcore = mpcore::RegisterBlock::new(); let mpcore = mpcore::RegisterBlock::mpcore();
mpcore.scu_invalidate.invalidate_all_cores(); mpcore.scu_invalidate.invalidate_all_cores();
zero_bss(&mut __bss_start, &mut __bss_end); zero_bss(&mut __bss_start, &mut __bss_end);
@ -68,7 +68,7 @@ unsafe fn boot_core0() -> ! {
unsafe fn boot_core1() -> ! { unsafe fn boot_core1() -> ! {
l1_cache_init(); l1_cache_init();
let mpcore = mpcore::RegisterBlock::new(); let mpcore = mpcore::RegisterBlock::mpcore();
mpcore.scu_invalidate.invalidate_core1(); mpcore.scu_invalidate.invalidate_core1();
let mmu_table = mmu::L1Table::get(); let mmu_table = mmu::L1Table::get();