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zynq::flash: add missing config bits to enable addressing mode

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This commit is contained in:
Astro 2019-11-28 03:02:51 +01:00
parent a199a5dc7d
commit 5642feb824
2 changed files with 31 additions and 10 deletions
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36
src/zynq/flash/mod.rs
View File

@ -1,5 +1,6 @@
//! Quad-SPI Flash Controller //! Quad-SPI Flash Controller
use core::marker::PhantomData;
use crate::regs::{RegisterW, RegisterRW}; use crate::regs::{RegisterW, RegisterRW};
use super::slcr; use super::slcr;
use super::clocks::CpuClocks; use super::clocks::CpuClocks;
@ -8,23 +9,25 @@ pub mod regs;
const FLASH_BAUD_RATE: u32 = 50_000_000; const FLASH_BAUD_RATE: u32 = 50_000_000;
pub struct LinearAddressing;
/// Flash Interface Driver /// Flash Interface Driver
/// ///
/// For 2x Spansion S25FL128SAGMFIR01 /// For 2x Spansion S25FL128SAGMFIR01
pub struct Flash { pub struct Flash<MODE> {
regs: &'static mut regs::RegisterBlock, regs: &'static mut regs::RegisterBlock,
_mode: PhantomData<MODE>,
} }
impl Flash { impl Flash<()> {
pub fn new(clock: u32) -> Self { pub fn new(clock: u32) -> Self {
Self::enable_clocks(clock); Self::enable_clocks(clock);
Self::setup_signals(); Self::setup_signals();
Self::reset(); Self::reset();
let regs = regs::RegisterBlock::qspi(); let regs = regs::RegisterBlock::qspi();
let mut flash = Flash { regs }; let mut flash = Flash { regs, _mode: PhantomData };
flash.configure((FLASH_BAUD_RATE - 1 + clock) / FLASH_BAUD_RATE); flash.configure((FLASH_BAUD_RATE - 1 + clock) / FLASH_BAUD_RATE);
flash.setup_linear_addressing_mode();
flash flash
} }
@ -106,25 +109,40 @@ impl Flash {
baud_rate_div += 1; baud_rate_div += 1;
} }
self.regs.config.modify(|_, w| w self.regs.config.write(regs::Config::zeroed()
.baud_rate_div(baud_rate_div as u8) .baud_rate_div(baud_rate_div as u8)
.mode_sel(true) .mode_sel(true)
.leg_flsh(true) .leg_flsh(true)
.endian(false)
.fifo_width(0b11) .fifo_width(0b11)
); );
} }
fn setup_linear_addressing_mode(&mut self) { pub fn linear_addressing_mode(self) -> Flash<LinearAddressing> {
self.regs.lqspi_cfg.modify(|_, w| w // Set manual start enable to auto mode.
// Assert the chip select.
self.regs.config.modify(|_, w| w
.man_start_en(false)
.pcs(false)
);
self.regs.lqspi_cfg.write(regs::LqspiCfg::zeroed()
.inst_code(0x3) .inst_code(0x3)
.u_page(false) .u_page(false)
.sep_bus(false) .sep_bus(false)
.two_mem(false) .two_mem(false)
.lq_mode(true) .lq_mode(true)
); );
}
self.regs.enable.modify(|_, w| w.spi_en(true));
Flash {
regs: self.regs,
_mode: PhantomData,
}
}
}
impl Flash<LinearAddressing> {
pub fn ptr<T>(&mut self) -> *mut T { pub fn ptr<T>(&mut self) -> *mut T {
0xFC00_0000 as *mut _ 0xFC00_0000 as *mut _
} }

5
src/zynq/flash/regs.rs
View File

@ -9,7 +9,7 @@ pub struct RegisterBlock {
pub intr_en: RW<u32>, pub intr_en: RW<u32>,
pub intr_dis: RW<u32>, pub intr_dis: RW<u32>,
pub intr_mask: RO<u32>, pub intr_mask: RO<u32>,
pub enable: RW<u32>, pub enable: Enable,
pub delay: RW<u32>, pub delay: RW<u32>,
pub txd0: WO<u32>, pub txd0: WO<u32>,
pub rx_data: RO<u32>, pub rx_data: RO<u32>,
@ -77,6 +77,9 @@ register_bit!(config,
/// false: legacy SPI mode, true: Flash memory interface mode /// false: legacy SPI mode, true: Flash memory interface mode
leg_flsh, 31); leg_flsh, 31);
register!(enable, Enable, RW, u32);
register_bit!(enable, spi_en, 0);
register!(lqspi_cfg, LqspiCfg, RW, u32); register!(lqspi_cfg, LqspiCfg, RW, u32);
register_bits!(lqspi_cfg, inst_code, u8, 0, 7); register_bits!(lqspi_cfg, inst_code, u8, 0, 7);
register_bits!(lqspi_cfg, dummy_byte, u8, 8, 10); register_bits!(lqspi_cfg, dummy_byte, u8, 8, 10);