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zynq-rs
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zynq::ddr: use different data_bus_width for targets 

DDR still works only on the zc706, not on the cora z7-10.
This commit is contained in:
Astro 2019-11-11 00:06:35 +01:00
parent cae02947bc
commit 4d3b2ac7e5
1 changed files with 5 additions and 1 deletions
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6
src/zynq/ddr/mod.rs
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@ -169,10 +169,14 @@ impl DdrRam {
self.regs.ddrc_ctrl.modify(|_, w| w self.regs.ddrc_ctrl.modify(|_, w| w
.soft_rstb(false) .soft_rstb(false)
); );
#[cfg(feature = "target_zc706")]
let width = regs::DataBusWidth::Width32bit;
#[cfg(feature = "target_cora_z7_10")]
let width = regs::DataBusWidth::Width16bit;
self.regs.ddrc_ctrl.modify(|_, w| w self.regs.ddrc_ctrl.modify(|_, w| w
.soft_rstb(true) .soft_rstb(true)
.powerdown_en(false) .powerdown_en(false)
.data_bus_width(regs::DataBusWidth::Width32bit) .data_bus_width(width)
); );
while self.status() == regs::ControllerStatus::Init {} while self.status() == regs::ControllerStatus::Init {}