forked from M-Labs/zynq-rs
zynq::ddr: use different data_bus_width for targets
DDR still works only on the zc706, not on the cora z7-10.
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@ -169,10 +169,14 @@ impl DdrRam {
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self.regs.ddrc_ctrl.modify(|_, w| w
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.soft_rstb(false)
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);
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#[cfg(feature = "target_zc706")]
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let width = regs::DataBusWidth::Width32bit;
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#[cfg(feature = "target_cora_z7_10")]
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let width = regs::DataBusWidth::Width16bit;
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self.regs.ddrc_ctrl.modify(|_, w| w
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.soft_rstb(true)
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.powerdown_en(false)
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.data_bus_width(regs::DataBusWidth::Width32bit)
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.data_bus_width(width)
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);
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while self.status() == regs::ControllerStatus::Init {}
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