forked from M-Labs/zynq-rs
define core1 stack in linker script
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1c270a55e2
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3948021458
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@ -46,10 +46,16 @@ SECTIONS
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__bss_end = .;
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} > OCM
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.stack (NOLOAD) : ALIGN(8) {
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__stack_end = .;
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.stack1 (NOLOAD) : ALIGN(8) {
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__stack1_end = .;
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. += 0x200;
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__stack1_start = .;
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} > OCM
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.stack0 (NOLOAD) : ALIGN(8) {
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__stack0_end = .;
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. = ORIGIN(OCM) + LENGTH(OCM) - 8;
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__stack_start = .;
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__stack0_start = .;
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} > OCM
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/DISCARD/ :
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@ -61,4 +67,4 @@ SECTIONS
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}
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}
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ASSERT(SIZEOF(.stack) >= 0x8000, "less than 32 KB left for stack");
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ASSERT(SIZEOF(.stack0) >= 0x8000, "less than 32 KB left for stack");
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@ -32,8 +32,6 @@ mod ps7_init;
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const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
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static mut STACK_CORE1: [u32; 512] = [0; 512];
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#[no_mangle]
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pub fn main_core0() {
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// zynq::clocks::CpuClocks::enable_io(1_250_000_000);
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@ -143,9 +141,7 @@ pub fn main_core0() {
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tx.async_send(None).await;
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});
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let core1_stack = unsafe { &mut STACK_CORE1[..] };
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println!("{} bytes stack for core1", core1_stack.len());
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let core1 = boot::Core1::start(core1_stack);
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let core1 = boot::Core1::start();
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let (mut core1_req, rx) = sync_channel(10);
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*CORE1_REQ.lock() = Some(rx);
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@ -160,13 +156,6 @@ pub fn main_core0() {
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});
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core1.disable();
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libcortex_a9::asm::dsb();
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print!("Core1 stack [{:08X}..{:08X}]:", &core1.stack[0] as *const _ as u32, &core1.stack[core1.stack.len() - 1] as *const _ as u32);
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for w in core1.stack {
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print!(" {:08X}", w);
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}
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println!(".");
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let eth = zynq::eth::Eth::default(HWADDR.clone());
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println!("Eth on");
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@ -9,13 +9,13 @@ use libboard_zynq::{slcr, mpcore};
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extern "C" {
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static mut __bss_start: u32;
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static mut __bss_end: u32;
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static mut __stack_start: u32;
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static mut __stack0_start: u32;
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static mut __stack1_start: u32;
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fn main_core0();
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fn main_core1();
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}
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/// `0` means: wait for initialization by core0
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static mut CORE1_STACK: VolatileCell<u32> = VolatileCell::new(0);
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static mut CORE1_ENABLED: VolatileCell<bool> = VolatileCell::new(false);
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#[link_section = ".text.boot"]
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#[no_mangle]
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@ -25,15 +25,14 @@ pub unsafe extern "C" fn _boot_cores() -> ! {
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match MPIDR.read() & CORE_MASK {
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0 => {
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SP.write(&mut __stack_start as *mut _ as u32);
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SP.write(&mut __stack0_start as *mut _ as u32);
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boot_core0();
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}
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1 => {
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while CORE1_STACK.get() == 0 {
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while !CORE1_ENABLED.get() {
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asm::wfe();
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}
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SP.write(CORE1_STACK.get());
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SP.write(&mut __stack1_start as *mut _ as u32);
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boot_core1();
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}
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_ => unreachable!(),
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@ -104,18 +103,12 @@ fn l1_cache_init() {
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dciall();
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}
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pub struct Core1<S: AsMut<[u32]>> {
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pub stack: S,
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pub struct Core1 {
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}
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impl<S: AsMut<[u32]>> Core1<S> {
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impl Core1 {
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/// Reset and start core1
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///
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/// The stack must be in OCM because core1 still has to
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/// initialize its MMU before it can access DDR.
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pub fn start(stack: S) -> Self {
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let mut core = Core1 { stack };
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pub fn start() -> Self {
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// reset and stop (safe to repeat)
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_rst1(true));
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@ -123,15 +116,13 @@ impl<S: AsMut<[u32]>> Core1<S> {
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_rst1(false));
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});
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let stack = core.stack.as_mut();
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let stack_start = &mut stack[stack.len() - 1];
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unsafe {
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CORE1_STACK.set(stack_start as *mut _ as u32);
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CORE1_ENABLED.set(true);
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}
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// Ensure stack pointer has been written to cache
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asm::dmb();
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// Flush cache-line
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cache::dccmvac(unsafe { &CORE1_STACK } as *const _ as usize);
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cache::dccmvac(unsafe { &CORE1_ENABLED } as *const _ as usize);
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// wake up core1
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slcr::RegisterBlock::unlocked(|slcr| {
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@ -139,12 +130,12 @@ impl<S: AsMut<[u32]>> Core1<S> {
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_clkstop1(false));
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});
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core
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Core1 {}
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}
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pub fn disable(&self) {
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unsafe {
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CORE1_STACK.set(0);
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CORE1_ENABLED.set(false);
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}
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self.restart();
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}
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