fsagbuya/zynq-rs
1
0
Fork 0
forked from M-Labs/zynq-rs
Code Pull Requests Activity

zynq::ddr: fix PLL_FDIV_LOCK_PARAM usage

Browse Source 
this seems to make DDR RAM work.
This commit is contained in:
Astro 2019-10-27 20:30:38 +01:00
parent 9b4f07f37c
commit 27114aec62
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/zynq/clocks.rs
View File

@ -102,7 +102,7 @@ impl CpuClocks {
);
let (pll_res, pll_cp, lock_cnt) = PLL_FDIV_LOCK_PARAM.iter()
.filter(|(fdiv_max, _)| fdiv <= *fdiv_max)
.last()
.nth(0)
.expect("PLL_FDIV_LOCK_PARAM")
.1.clone();
regs.ddr_pll_cfg.write(