forked from M-Labs/zynq-rs
delint
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parent
e135b27c13
commit
1f9ad5ff62
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@ -1,4 +1,3 @@
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use core::mem::uninitialized;
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use bit_field::BitField;
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use super::{regs::*, asm};
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use crate::regs::RegisterW;
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@ -73,7 +72,7 @@ pub struct L1Entry(u32);
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impl L1Entry {
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#[inline(always)]
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pub fn section(phys_base: u32, section: L1Section) -> Self {
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/// Must be aligned to 1 MB
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// Must be aligned to 1 MB
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assert!(phys_base & 0x000f_ffff == 0);
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let mut entry = L1Entry(phys_base);
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@ -382,8 +381,4 @@ pub fn with_mmu<F: FnMut() -> !>(l1table: &L1Table, mut f: F) -> ! {
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asm::isb();
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f();
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// table must live until here
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drop(l1table.table);
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unreachable!();
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}
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@ -1,5 +1,5 @@
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use crate::{register_bit, register_bits};
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use crate::regs::{RegisterR, RegisterW, RegisterRW};
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use crate::regs::{RegisterR, RegisterW};
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macro_rules! def_reg_r {
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($name:tt, $type: ty, $asm_instr:tt) => {
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@ -219,7 +219,7 @@ impl<RX, TX> Eth<RX, TX> {
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});
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}
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fn init(mut self) -> Self {
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fn init(self) -> Self {
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// Clear the Network Control register.
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self.regs.net_ctrl.write(regs::NetCtrl::zeroed());
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self.regs.net_ctrl.write(regs::NetCtrl::zeroed().clear_stat_regs(true));
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@ -1,6 +1,6 @@
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use volatile_register::{RO, WO, RW};
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use crate::{register, register_bit, register_bits, register_bits_typed, regs::*};
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use crate::{register, register_bit, register_bits, register_bits_typed};
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#[repr(C)]
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pub struct RegisterBlock {
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@ -1,5 +1,5 @@
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use core::ops::Deref;
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use crate::{register, register_bit, register_bits, register_bits_typed, regs::*};
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use crate::{register, register_bit, register_bits, regs::*};
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use super::MTU;
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#[derive(Debug)]
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@ -18,10 +18,12 @@ pub struct DescEntry {
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}
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register!(desc_word0, DescWord0, RW, u32);
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/// true if owned by software, false if owned by hardware
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register_bit!(desc_word0, used, 0);
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/// mark last desc in list
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register_bit!(desc_word0, wrap, 1);
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register_bit!(desc_word0,
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/// true if owned by software, false if owned by hardware
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used, 0);
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register_bit!(desc_word0,
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/// mark last desc in list
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wrap, 1);
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register_bits!(desc_word0, address, u32, 2, 31);
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register!(desc_word1, DescWord1, RW, u32);
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@ -1,5 +1,5 @@
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use core::ops::{Deref, DerefMut};
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use crate::{register, register_bit, register_bits, register_bits_typed, regs::*};
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use crate::{register, register_bit, register_bits, regs::*};
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use crate::println;
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use super::{MTU, regs};
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@ -20,10 +20,12 @@ register_bits!(desc_word1, csum_offload_errors, u8, 20, 22);
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register_bit!(desc_word1, late_collision_tx_error, 26);
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register_bit!(desc_word1, ahb_frame_corruption, 27);
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register_bit!(desc_word1, retry_limit_exceeded, 29);
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/// marks last descriptor in list
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register_bit!(desc_word1, wrap, 30);
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/// true if owned by software, false if owned by hardware
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register_bit!(desc_word1, used, 31);
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register_bit!(desc_word1,
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/// marks last descriptor in list
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wrap, 30);
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register_bit!(desc_word1,
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/// true if owned by software, false if owned by hardware
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used, 31);
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/// Number of descriptors
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pub const DESCS: usize = 8;
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@ -5,6 +5,8 @@
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#![feature(naked_functions)]
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#![feature(compiler_builtins_lib)]
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#![feature(never_type)]
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// TODO: disallow unused/dead_code when code moves into a lib crate
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#![allow(dead_code)]
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use core::mem::uninitialized;
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@ -79,7 +81,7 @@ fn main() {
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let mut rx_descs: [eth::rx::DescEntry; 8] = unsafe { uninitialized() };
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let mut rx_buffers = [[0u8; 1536]; 8];
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let mut eth = eth.start_rx(&mut rx_descs, &mut rx_buffers);
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let eth = eth.start_rx(&mut rx_descs, &mut rx_buffers);
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let mut tx_descs: [eth::tx::DescEntry; 8] = unsafe { uninitialized() };
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let mut tx_buffers = [[0u8; 1536]; 8];
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let mut eth = eth.start_tx(&mut tx_descs, &mut tx_buffers);
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@ -111,7 +113,6 @@ fn main() {
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None => println!("eth tx shortage"),
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}
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}
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panic!("End");
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}
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#[panic_handler]
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@ -1,6 +1,6 @@
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///! Register definitions for System Level Control
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use volatile_register::{RO, WO, RW};
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use volatile_register::{RO, RW};
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use crate::{register, register_at,
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register_bit, register_bits, register_bits_typed,
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regs::RegisterW, regs::RegisterRW};
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@ -9,7 +9,7 @@ pub fn get_uart() -> &'static mut Uart {
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unsafe {
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match &mut UART {
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None => {
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let mut uart = Uart::serial(UART_RATE);
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let uart = Uart::serial(UART_RATE);
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UART = Some(uart);
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UART.as_mut().unwrap()
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}
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@ -23,7 +23,7 @@ macro_rules! print {
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($($arg:tt)*) => ({
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use core::fmt::Write;
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let uart = crate::stdio::get_uart();
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write!(uart, $($arg)*);
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let _ = write!(uart, $($arg)*);
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})
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}
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@ -32,8 +32,8 @@ macro_rules! println {
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($($arg:tt)*) => ({
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use core::fmt::Write;
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let uart = crate::stdio::get_uart();
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write!(uart, $($arg)*);
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write!(uart, "\r\n");
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let _ = write!(uart, $($arg)*);
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let _ = write!(uart, "\r\n");
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while !uart.tx_fifo_empty() {}
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})
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}
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@ -37,7 +37,7 @@ pub fn configure(regs: &mut RegisterBlock, mut clk: u32, baud: u32) {
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}
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match best {
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Some((cd, bdiv, error)) => {
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Some((cd, bdiv, _error)) => {
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regs.baud_rate_gen.write(BaudRateGen::zeroed().cd(cd));
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regs.baud_rate_divider.write(BaudRateDiv::zeroed().bdiv(bdiv));
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}
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@ -1,5 +1,4 @@
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use core::fmt;
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use volatile_register::RW;
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use crate::regs::*;
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use crate::slcr;
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@ -1,6 +1,6 @@
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use volatile_register::{RO, WO, RW};
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use crate::{register, register_bit, register_bits, register_bits_typed, register_at, regs::*};
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use crate::{register, register_bit, register_bits, register_bits_typed, register_at};
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#[repr(u8)]
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pub enum ChannelMode {
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