forked from M-Labs/zynq-rs
libsupport_zynq/boot: fix cache mainteinance opertaions
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283bc9b810
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1ba0aa450f
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@ -4,7 +4,7 @@ use libregister::{
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VolatileCell,
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RegisterR, RegisterW, RegisterRW,
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};
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use libcortex_a9::{asm, regs::*, cache, mmu, spin_lock_yield, notify_spin_lock};
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use libcortex_a9::{asm, l2c, regs::*, cache, mmu, spin_lock_yield, notify_spin_lock};
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use libboard_zynq::{slcr, mpcore};
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extern "C" {
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@ -101,7 +101,7 @@ fn l1_cache_init() {
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// for all of the L1 data cache rather than a (previously
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// unspecified) combination of one cache set and one cache
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// way.
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dciall();
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dciall_l1();
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}
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pub struct Core1 {
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@ -131,12 +131,13 @@ impl Core1 {
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unsafe {
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CORE1_ENABLED.set(true);
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}
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// Ensure values have been written to cache
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asm::dmb();
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// Flush cache-line
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cache::dccmvac(unsafe { &CORE1_ENABLED } as *const _ as usize);
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cache::dcc(unsafe { &CORE1_ENABLED });
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if sdram {
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cache::dccmvac(0);
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asm::dsb();
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l2c::l2_cache_clean(0);
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l2c::l2_cache_sync();
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}
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// wake up core1
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