main: start_core1

src/boot.rs

@@ -101,3 +101,14 @@ fn l1_cache_init() {
     //       way.
     dciall();
 }
+
+pub fn start_core1<T: AsMut<[u32]>>(mut stack: T) {
+    let stack = stack.as_mut();
+    let stack_start = &mut stack[stack.len() - 1];
+    unsafe {
+        CORE1_STACK = stack_start as *mut _ as u32;
+    }
+
+    // wake up core1
+    asm::sev();
+}

src/main.rs

@@ -36,6 +36,10 @@ pub fn main() {
     ddr.memtest();
     ram::init_alloc(&mut ddr);
 
+    let core1_stack = vec![0; 2048];
+    println!("{} bytes stack for core1", core1_stack.len());
+    boot::start_core1(core1_stack);
+
     let eth = zynq::eth::Eth::default(HWADDR.clone());
     println!("Eth on");