fd125a506f
gateware: sys freq 100MHz -> 125MHz
2025-01-13 11:20:48 +08:00
0ca6ac1354
gateware: use LTC2195 dco clk as PL only clock source
2025-01-13 11:17:42 +08:00
d9d44fa9e8
gateware: use si5340 to generate PL's rst
2025-01-13 11:17:42 +08:00
bec032ab75
gateware: Add sys_clk_double clk domain
2025-01-13 11:17:23 +08:00
a5dc232be4
gateware: add cdc fifo for dac output value override csr
2024-11-15 15:42:25 +08:00
87059eef2b
gateware: async fifo with depth of 2 is broken
...
- Changing depth to 4 has resolved cdc issue
2024-11-15 15:42:25 +08:00
8a40bb4f21
gateware: Add cdc fifo for adc and dac
...
- dco2d and sys clk use two different clock sources
2024-11-13 15:43:35 +08:00
6cef418756
gateware: Add CSR Ctrl to PL's MMCM
...
- Generate 45 Degree Phase Shifted DDR Clock
- PLLE2_Base -> MMCM_ADV for ddr clock dynamic phase shift
- Add mmcm_rst, ddr_clk_ps, mmcm_locked status to CSR
- Generate dco2d rst signal from mmcm and connect to the related logic
2024-11-08 16:33:17 +08:00
1244c84f67
fix typo
2024-03-06 17:53:13 +08:00
cd9590503c
add fast-servo gateware support files
2024-03-01 16:39:56 +08:00
