Commit Graph

6 Commits

Author SHA1 Message Date
fd125a506f gateware: sys freq 100MHz -> 125MHz 2025-01-13 11:20:48 +08:00
0ca6ac1354 gateware: use LTC2195 dco clk as PL only clock source 2025-01-13 11:17:42 +08:00
d9d44fa9e8 gateware: use si5340 to generate PL's rst 2025-01-13 11:17:42 +08:00
bec032ab75 gateware: Add sys_clk_double clk domain 2025-01-13 11:17:23 +08:00
8a40bb4f21 gateware: Add cdc fifo for adc and dac
- dco2d and sys clk use two different clock sources
2024-11-13 15:43:35 +08:00
cd9590503c add fast-servo gateware support files 2024-03-01 16:39:56 +08:00