forked from M-Labs/nix-servo
apply original dac script
This commit is contained in:
parent
ba07d6a7de
commit
86e441a487
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@ -1,24 +1,11 @@
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# This file is part of Fast Servo Software Package.
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import mmap
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#
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import os
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# Copyright (C) 2023 Jakub Matyas
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import logging
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# Warsaw University of Technology <jakubk.m@gmail.com>
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <https://www.gnu.org/licenses/>.
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import time
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import time
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logging.basicConfig(level=logging.INFO)
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logger = logging.getLogger(__name__)
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import spidev
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import spidev
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from pyfastservo.common import (
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from pyfastservo.common import (
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CH0_HIGH_WORD_ADDR,
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CH0_HIGH_WORD_ADDR,
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@ -28,13 +15,12 @@ from pyfastservo.common import (
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CTRL_ADDR,
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CTRL_ADDR,
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MAP_MASK,
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MAP_MASK,
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PAGESIZE,
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PAGESIZE,
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write_to_memory,
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read_from_memory
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)
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)
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# /dev/spidev2.0 <=> spidev<BUS>.<DEVICE>
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# /dev/spidev2.0 <=> spidev<BUS>.<DEVICE>
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MAIN_DAC_BUS = 2
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MAIN_DAC_BUS = 2
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MAIN_DAC_DEVICE = 0
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MAIN_DAC_DEVICE = 0
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DAC_VERSION = 0x0A
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DAC_VERSION = 0x0A
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@ -46,40 +32,190 @@ def spi_read(spi, address):
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return rx_buffer[1]
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return rx_buffer[1]
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def hard_reset(spi):
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def hard_reset(spi):
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spi_write(spi, 0x00, 0x20) # Software reset
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spi_write(spi, 0x00, 0x10) # Software reset
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spi_write(spi, 0x00, 0x00) # Release software reset
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spi_write(spi, 0x00, 0x00) # Release software reset
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spi_read(spi, 0x00) # Read reset address (necessary for reset to take effect)
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spi_read(spi, 0x00) # Read reset address (necessary for reset to take effect)
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def check_version(spi):
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def check_version(spi):
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version = spi_read(spi, 0x1F)
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version = spi_read(spi, 0x1F)
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print(f"DAC version: 0x{version:02X}")
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if version == DAC_VERSION:
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return version == DAC_VERSION
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print(f"Verified DAC version: 0x{version:02X}")
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else:
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print(f"Unrecognized device version: 0x{version:02X}")
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def configure_dac(spi):
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def set_data_control_and_output_mode(spi, mode='differential'):
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power_down_reg = spi_read(spi, 0x01)
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try:
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spi_write(spi, 0x01, power_down_reg & ~(1 << 0)) # Clear EXTREF bit for internal reference
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current_reg = spi_read(spi, 0x02)
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spi_write(spi, 0x0D, 0x00) # Set RREF to 10 kΩ for 1.0V reference
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logger.info(f"Current data control register value: 0x{current_reg:02X}")
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spi_write(spi, 0x04, 0xA0) # Enable on-chip IRSET (1.6 kΩ for 20mA output)
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spi_write(spi, 0x07, 0xA0) # Enable on-chip QRSET (1.6 kΩ for 20mA output)
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spi_write(spi, 0x05, 0x00) # Disable internal IRCML
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spi_write(spi, 0x08, 0x00) # Disable internal QRCML
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spi_write(spi, 0x02, 0xB4) # Enable 2's complement, LVDS interface, 4 LVDS lanes
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def dac_self_calibration(spi):
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new_reg = 0xB4
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spi_write(spi, 0x12, 0x00) # Reset calibration status
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spi_write(spi, 0x0E, 0x08) # Enable calibration clock, default divide ratio
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spi_write(spi, 0x0E, 0x38) # CALSELI = 1, CALSELQ = 1, CALCLK = 1
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spi_write(spi, 0x12, 0x10) # Set CALEN bit
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while True:
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if mode == 'differential':
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status = spi_read(spi, 0x0F)
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new_reg &= ~0x03
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if status & 0xC0 == 0xC0: # Both CALSTATI and CALSTATQ are 1
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elif mode == 'single_ended':
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new_reg = (new_reg & ~0x01) | 0x02
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else:
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logger.error(f"Invalid output mode: {mode}")
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return
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spi_write(spi, 0x02, new_reg)
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verify_reg = spi_read(spi, 0x02)
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if verify_reg == new_reg:
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logger.info(f"Data control set and output mode successfully set to {mode}")
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logger.info(f"New data control register value: 0x{verify_reg:02X}")
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else:
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logger.error(f"Failed to set data control and output mode. Expected: 0x{new_reg:02X}, Got: 0x{verify_reg:02X}")
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except Exception as e:
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logger.error(f"Error setting data control and output mode: {e}")
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def wait_for_clock_sync(spi):
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max_attempts = 10
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for attempt in range(max_attempts):
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clkmode = spi_read(spi, 0x14)
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if not clkmode & 0x10:
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print(f"Clock synchronized after {attempt + 1} attempts")
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break
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break
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time.sleep(0.01)
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if attempt == max_attempts - 1:
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print("Warning: Clock synchronization not achieved")
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time.sleep(0.001)
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def enable_dac_outputs(spi):
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try:
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# Read current power-down register value
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power_down_reg = spi_read(spi, 0x01)
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logger.info(f"Current power-down register value: 0x{power_down_reg:02X}")
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if not (power_down_reg & ((1 << 4) | (1 << 3))):
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logger.info("DAC outputs are already enabled")
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return
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new_power_down_reg = power_down_reg & ~((1 << 4) | (1 << 3))
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spi_write(spi, 0x01, new_power_down_reg)
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# Verify the write operation
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verify_power_down_reg = spi_read(spi, 0x01)
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if verify_power_down_reg == new_power_down_reg:
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logger.info("DAC outputs successfully enabled")
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else:
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logger.error(f"Failed to enable DAC outputs. Expected: 0x{new_power_down_reg:02X}, Got: 0x{verify_power_down_reg:02X}")
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except Exception as e:
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logger.error(f"Error enabling DAC outputs: {e}")
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def set_dac_constant_output(value=0xFFFF):
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try:
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max_value = 0x3FFF # 14-bit maximum (2^14 - 1)
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value = min(value, max_value)
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# Split the value into high and low words
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low_word_value = value & 0xFF
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high_word_value = (value >> 8) & 0x3F
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# Write to Channel 0
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write_to_memory(CH0_HIGH_WORD_ADDR, high_word_value)
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write_to_memory(CH0_LOW_WORD_ADDR, low_word_value)
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# Write to Channel 1
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write_to_memory(CH1_HIGH_WORD_ADDR, high_word_value)
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write_to_memory(CH1_LOW_WORD_ADDR, low_word_value)
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logger.info(f"DAC outputs set to constant value: 0x{value:04X}")
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logger.info("Please verify the output using an oscilloscope")
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except Exception as e:
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logger.error(f"Error setting DAC constant output: {e}")
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def configure_dac_for_hardware(spi):
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try:
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# Enable internal reference
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power_down_reg = spi_read(spi, 0x01)
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power_down_reg &= ~(1 << 0) # Clear EXTREF bit for internal reference
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spi_write(spi, 0x01, power_down_reg)
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logger.info("Internal reference enabled")
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# Set RREF to default 10 kΩ for 1.0V reference
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spi_write(spi, 0x0D, 0x00)
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logger.info("RREF set to 10 kΩ for 1.0V reference")
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# Enable on-chip IRSET and QRSET
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irset_value = 0xA0 # 10100000
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spi_write(spi, 0x04, irset_value) # IRSET
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spi_write(spi, 0x07, irset_value) # QRSET
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# Disable internal termination resistors
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ircml_value = 0x00
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spi_write(spi, 0x05, ircml_value) # IRCML
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spi_write(spi, 0x08, ircml_value) # QRCML
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spi_write(spi, 0x02, 0xB4)
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# Verify settings
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irset_read = spi_read(spi, 0x04)
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qrset_read = spi_read(spi, 0x07)
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ircml_read = spi_read(spi, 0x05)
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qrcml_read = spi_read(spi, 0x08)
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data_control_read = spi_read(spi, 0x02)
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if (irset_read == irset_value and qrset_read == irset_value and
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ircml_read == ircml_value and qrcml_read == ircml_value and
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data_control_read == 0xB4):
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logger.info("DAC configured for 20mA output with external termination")
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else:
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logger.error(f"DAC configuration failed. IRSET: 0x{irset_read:02X}, QRSET: 0x{qrset_read:02X}, "
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f"IRCML: 0x{ircml_read:02X}, QRCML: 0x{qrcml_read:02X}, "
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f"Data Control: 0x{data_control_read:02X}")
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except Exception as e:
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logger.error(f"Error configuring DAC: {e}")
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def read_from_memory(address, n_bytes):
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assert n_bytes <= 4
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addr = address
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try:
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f = os.open("/dev/mem", os.O_SYNC | os.O_RDWR)
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with mmap.mmap(
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f,
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PAGESIZE,
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mmap.MAP_SHARED,
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mmap.PROT_READ | mmap.PROT_WRITE,
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offset=addr & ~MAP_MASK,
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) as mem:
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start_addr = addr & MAP_MASK
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stop_addr = start_addr + 4
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# print(f"addr: 0x{addr:x}\tstart_addr: 0x{start_addr}\tstop_addr: 0x{stop_addr}")
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contents = mem[start_addr:stop_addr]
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read_value = list(contents)[:n_bytes]
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finally:
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os.close(f)
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return read_value
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def write_to_memory(address, value):
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value_bytes = value.to_bytes(4, "little")
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addr = address
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try:
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f = os.open("/dev/mem", os.O_SYNC | os.O_RDWR)
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with mmap.mmap(
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f,
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PAGESIZE,
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mmap.MAP_SHARED,
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mmap.PROT_READ | mmap.PROT_WRITE,
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offset=addr & ~MAP_MASK,
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) as mem:
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start_addr = addr & MAP_MASK
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stop_addr = start_addr + 4
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mem[start_addr:stop_addr] = value_bytes
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contents = mem[start_addr:stop_addr]
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finally:
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os.close(f)
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spi_write(spi, 0x12, 0x00) # Clear calibration bits
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spi_write(spi, 0x0E, 0x30) # Keep CALSELI and CALSELQ set, clear CALCLK
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print("DAC self-calibration completed")
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def manual_override(enable=True):
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def manual_override(enable=True):
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reg_contents = read_from_memory(CTRL_ADDR, 1)[0]
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reg_contents = read_from_memory(CTRL_ADDR, 1)[0]
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@ -87,6 +223,7 @@ def manual_override(enable=True):
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to_write = reg_contents | 0b1 if enable else reg_contents & 0b110
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to_write = reg_contents | 0b1 if enable else reg_contents & 0b110
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write_to_memory(CTRL_ADDR, to_write)
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write_to_memory(CTRL_ADDR, to_write)
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def power_down(channel, power_down=True):
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def power_down(channel, power_down=True):
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assert channel in (0, 1)
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assert channel in (0, 1)
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@ -100,46 +237,42 @@ def power_down(channel, power_down=True):
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reg_contents = read_from_memory(CTRL_ADDR, 1)[0]
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reg_contents = read_from_memory(CTRL_ADDR, 1)[0]
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print(f"REG contents: 0b{reg_contents:03b}")
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print(f"REG contents: 0b{reg_contents:03b}")
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def set_dac_output(value):
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value = min(value, 0x3FFF)
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low_word = value & 0xFF
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high_word = (value >> 8) & 0x3F
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write_to_memory(CH0_HIGH_WORD_ADDR, high_word)
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write_to_memory(CH0_LOW_WORD_ADDR, low_word)
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write_to_memory(CH1_HIGH_WORD_ADDR, high_word)
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write_to_memory(CH1_LOW_WORD_ADDR, low_word)
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print(f"DAC output set to: 0x{value:04X}")
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def configure_ad9117():
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def configure_ad9117():
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spi = spidev.SpiDev()
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spi = spidev.SpiDev()
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spi.open(MAIN_DAC_BUS, MAIN_DAC_DEVICE)
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spi.max_speed_hz = 5000
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spi.mode = 0b00 # CPOL = 0 CPHA = 0
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spi.cshigh = False
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try:
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try:
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spi.open(MAIN_DAC_BUS, MAIN_DAC_DEVICE)
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spi.max_speed_hz = 5000
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spi.mode = 0b00 # CPOL = 0 CPHA = 0
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spi.cshigh = False
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hard_reset(spi)
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hard_reset(spi)
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if not check_version(spi):
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check_version(spi)
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print("Unrecognized DAC version")
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return False
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configure_dac(spi)
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configure_dac_for_hardware(spi)
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# dac_self_calibration(spi)
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set_data_control_and_output_mode(spi, 'differential')
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wait_for_clock_sync(spi)
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# Enable DAC outputs
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enable_dac_outputs(spi)
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spi_write(spi, 0x01, spi_read(spi, 0x01) & ~((1 << 4) | (1 << 3)))
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power_down(0, False)
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power_down(0, False)
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power_down(1, False)
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power_down(1, False)
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manual_override(True)
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manual_override(True)
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print("AD9117 configuration completed successfully")
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set_dac_constant_output(0xFFFF)
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return True
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# Verify control register
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reg_contents = read_from_memory(CTRL_ADDR, 1)[0]
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logger.info(f"Control register contents after setting: 0b{reg_contents:03b}")
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# Verify channel settings
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ch0_high = read_from_memory(CH0_HIGH_WORD_ADDR, 1)[0]
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ch0_low = read_from_memory(CH0_LOW_WORD_ADDR, 1)[0]
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ch1_high = read_from_memory(CH1_HIGH_WORD_ADDR, 1)[0]
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ch1_low = read_from_memory(CH1_LOW_WORD_ADDR, 1)[0]
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logger.info(f"Channel 0: 0x{ch0_high:02X}{ch0_low:02X}, Channel 1: 0x{ch1_high:02X}{ch1_low:02X}")
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except Exception as e:
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except Exception as e:
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print(f"Error configuring AD9117: {e}")
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print(f"Error initializing DAC: {e}")
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return False
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finally:
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finally:
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spi.close()
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spi.close()
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@ -53,7 +53,7 @@ def perform_loopback_test(test_value):
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print(f"Expected: {test_value}, ADC: {adc_value}, DAC: {dac_value}")
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print(f"Expected: {test_value}, ADC: {adc_value}, DAC: {dac_value}")
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def main():
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def main():
|
||||||
test_value = 0x0FFF # Mid-range value (4095 in decimal)
|
test_value = 0x1FFF # Mid-range value (4095 in decimal)
|
||||||
perform_loopback_test(test_value)
|
perform_loopback_test(test_value)
|
||||||
|
|
||||||
if __name__ == "__main__":
|
if __name__ == "__main__":
|
||||||
|
|
Loading…
Reference in New Issue