nix-servo/fast-servo/linien-gateware/cores/adc.py

# This file is part of Fast Servo Software Package.
#
# Copyright (C) 2023 Jakub Matyas
# Warsaw University of Technology <jakubk.m@gmail.com>
# SPDX-License-Identifier: GPL-3.0-or-later
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
# 
# This program is distributed in the hope that it will be useful, 
# but WITHOUT ANY WARRANTY; without even the implied warranty of 
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <https://www.gnu.org/licenses/>.

from migen import *
from migen.genlib.cdc import MultiReg
from misoc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
from misoc.interconnect.stream import AsyncFIFO

class ADC(Module, AutoCSR):
    def __init__(self, platform):
        adc_pads = platform.request("adc")
        afe_pads = platform.request("adc_afe")

        self.frame_csr = CSRStatus(5)
        self.data_ch0 = CSRStatus(16)
        self.data_ch1 = CSRStatus(16)

        self.tap_delay = CSRStorage(5)
        self.bitslip_csr = CSRStorage(1)

        self.afe_ctrl = CSRStorage(7)

        tap_delay_val = Signal(5)
        bitslip = Signal()
        bitslip_re_dco_2d = Signal()

        ch1_gain_x10 = Signal()
        ch2_gain_x10 = Signal()
        ch1_shdn = Signal()
        ch2_shdn = Signal()

        self.data_out = [Signal(16, reset_less=True), Signal(16, reset_less=True)]
        self.s_frame = Signal(4)

        self.comb += [
            tap_delay_val.eq(self.tap_delay.storage),
            Cat(ch1_gain_x10, ch2_gain_x10, ch1_shdn, ch2_shdn).eq(
                self.afe_ctrl.storage[0:4]
            ),
        ]

        # self.comb += self.afe_ctrl.storage[4].eq(self.crg.mmcm_rst)
        # self.comb += self.afe_ctrl.storage[5].eq(self.crg.ddr_clk_phase_shift_en)
        # self.comb += self.afe_ctrl.storage[6].eq(self.crg.ddr_clk_phase_incdec)

        self.specials += MultiReg(self.bitslip_csr.re, bitslip_re_dco_2d, "sys")
        self.sync.sys += [
            bitslip.eq(Mux(bitslip_re_dco_2d, self.bitslip_csr.storage, 0))
        ]

        self.comb += [
            self.frame_csr.status[0:4].eq(self.s_frame[0:4]),
            # self.frame_csr.status[4].eq(self.crg.locked),
            self.data_ch0.status.eq(self.data_out[0]),
            self.data_ch1.status.eq(self.data_out[1]),
        ]

        self.comb += [
            afe_pads.ch1_gain.eq(ch1_gain_x10),
            afe_pads.ch2_gain.eq(ch2_gain_x10),
            afe_pads.nshdn_ch1.eq(~ch1_shdn),
            afe_pads.nshdn_ch2.eq(~ch2_shdn),
        ]

        dummy = Signal(8)
        dummy_idelay_rdy = Signal()

        self.specials += Instance(
            "LTC2195",
            i_rst_in=ResetSignal("sys"),
            i_clk200=ClockSignal("idelay"),
            i_DCO=ClockSignal("sys_double"),
            i_DCO_2D=ClockSignal("sys"),
            i_FR_in_p=adc_pads.frame_p,
            i_FR_in_n=adc_pads.frame_n,
            i_D0_in_p=adc_pads.data0_p,
            i_D0_in_n=adc_pads.data0_n,
            i_D1_in_p=adc_pads.data1_p,
            i_D1_in_n=adc_pads.data1_n,
            i_bitslip=bitslip,
            i_delay_val=tap_delay_val,
            o_ADC0_out=self.data_out[1],        # LANES swapped on hardware
            o_ADC1_out=self.data_out[0],
            o_FR_out=self.s_frame,
            o_o_data_from_pins=dummy,
            o_idelay_rdy=dummy_idelay_rdy,
        )


class AUX_ADC_CTRL(Module, AutoCSR):
    def __init__(self, platform):
        adc_aux_pads = platform.request("aux_adc")

        self.adc_aux_ctrl = CSRStorage(5)

        self.comb += [
            adc_aux_pads.diff_n.eq(~self.adc_aux_ctrl.storage[0]),
            adc_aux_pads.a.eq(self.adc_aux_ctrl.storage[1:4]),
            adc_aux_pads.range.eq(self.adc_aux_ctrl.storage[4]),
        ]