forked from M-Labs/nix-servo
266 lines
9.5 KiB
Coq
266 lines
9.5 KiB
Coq
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/**
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* $Id: axi_slave.v 961 2014-01-21 11:40:39Z matej.oblak $
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*
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* @brief Red Pitaya symplified AXI slave.
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*
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* @Author Matej Oblak
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*
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* (c) Red Pitaya http://www.redpitaya.com
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*
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* This part of code is written in Verilog hardware description language (HDL).
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* Please visit http://en.wikipedia.org/wiki/Verilog
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* for more details on the language used herein.
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*/
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/**
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* GENERAL DESCRIPTION:
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*
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* AXI slave used also for simple bus master.
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*
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*
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* /------\
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* WR ADDRESS ----> | WR |
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* WR DATA ----> | | -----------
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* WR RESPONSE <---- | CH | |
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* \------/ /--------\
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* | SIMPLE | ---> WR/RD ADDRRESS
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* AXI | | ---> WR DATA
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* | RP | <--- RD DATA
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* | BUS | <--- ACKNOWLEDGE
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* /------\ \--------/
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* RD ADDRESS ----> | RD | |
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* RD DATA <---- | CH | -----------
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* \------/
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*
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*
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* Because AXI bus is quite complex simplier bus was created.
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*
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* It combines write and read channel, where write has bigger priority. Command
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* is then send forward to red pitaya bus. When wite or read acknowledge is
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* received AXI response is created and new AXI is accepted.
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*
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* To prevent AXI lockups because no response is received, this slave creates its
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* own after 32 cycles (ack_cnt).
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*
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*/
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module axi_slave
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#(
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parameter AXI_DW = 64 , // data width (8,16,...,1024)
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parameter AXI_AW = 32 , // address width
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parameter AXI_IW = 8 , // ID width
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parameter AXI_SW = AXI_DW >> 3 // strobe width - 1 bit for every data byte
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)
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(
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// global signals
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input axi_clk_i , //!< AXI global clock
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input axi_rstn_i , //!< AXI global reset
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// axi write address channel
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input [ AXI_IW-1: 0] axi_awid_i , //!< AXI write address ID
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input [ AXI_AW-1: 0] axi_awaddr_i , //!< AXI write address
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input [ 4-1: 0] axi_awlen_i , //!< AXI write burst length
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input [ 3-1: 0] axi_awsize_i , //!< AXI write burst size
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input [ 2-1: 0] axi_awburst_i , //!< AXI write burst type
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input [ 2-1: 0] axi_awlock_i , //!< AXI write lock type
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input [ 4-1: 0] axi_awcache_i , //!< AXI write cache type
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input [ 3-1: 0] axi_awprot_i , //!< AXI write protection type
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input axi_awvalid_i , //!< AXI write address valid
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output axi_awready_o , //!< AXI write ready
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// axi write data channel
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input [ AXI_IW-1: 0] axi_wid_i , //!< AXI write data ID
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input [ AXI_DW-1: 0] axi_wdata_i , //!< AXI write data
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input [ AXI_SW-1: 0] axi_wstrb_i , //!< AXI write strobes
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input axi_wlast_i , //!< AXI write last
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input axi_wvalid_i , //!< AXI write valid
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output axi_wready_o , //!< AXI write ready
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// axi write response channel
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output [ AXI_IW-1: 0] axi_bid_o , //!< AXI write response ID
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output reg [ 2-1: 0] axi_bresp_o , //!< AXI write response
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output reg axi_bvalid_o , //!< AXI write response valid
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input axi_bready_i , //!< AXI write response ready
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// axi read address channel
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input [ AXI_IW-1: 0] axi_arid_i , //!< AXI read address ID
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input [ AXI_AW-1: 0] axi_araddr_i , //!< AXI read address
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input [ 4-1: 0] axi_arlen_i , //!< AXI read burst length
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input [ 3-1: 0] axi_arsize_i , //!< AXI read burst size
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input [ 2-1: 0] axi_arburst_i , //!< AXI read burst type
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input [ 2-1: 0] axi_arlock_i , //!< AXI read lock type
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input [ 4-1: 0] axi_arcache_i , //!< AXI read cache type
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input [ 3-1: 0] axi_arprot_i , //!< AXI read protection type
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input axi_arvalid_i , //!< AXI read address valid
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output axi_arready_o , //!< AXI read address ready
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// axi read data channel
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output [ AXI_IW-1: 0] axi_rid_o , //!< AXI read response ID
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output reg [ AXI_DW-1: 0] axi_rdata_o , //!< AXI read data
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output reg [ 2-1: 0] axi_rresp_o , //!< AXI read response
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output reg axi_rlast_o , //!< AXI read last
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output reg axi_rvalid_o , //!< AXI read response valid
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input axi_rready_i , //!< AXI read response ready
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// RP system read/write channel
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output [ AXI_AW-1: 0] sys_addr_o , //!< system bus read/write address.
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output [ AXI_DW-1: 0] sys_wdata_o , //!< system bus write data.
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output reg [ AXI_SW-1: 0] sys_sel_o , //!< system bus write byte select.
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output reg sys_wen_o , //!< system bus write enable.
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output reg sys_ren_o , //!< system bus read enable.
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input [ AXI_DW-1: 0] sys_rdata_i , //!< system bus read data.
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input sys_err_i , //!< system bus error indicator.
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input sys_ack_i //!< system bus acknowledge signal.
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);
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//---------------------------------------------------------------------------------
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//
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// AXI slave Module
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wire ack ;
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reg [ 6-1: 0] ack_cnt ;
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reg rd_do ;
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reg [ AXI_IW-1: 0] rd_arid ;
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reg [ AXI_AW-1: 0] rd_araddr ;
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reg rd_error ;
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wire rd_errorw ;
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reg wr_do ;
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reg [ AXI_IW-1: 0] wr_awid ;
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reg [ AXI_AW-1: 0] wr_awaddr ;
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reg [ AXI_IW-1: 0] wr_wid ;
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reg [ AXI_DW-1: 0] wr_wdata ;
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reg wr_error ;
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wire wr_errorw ;
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assign wr_errorw = (axi_awlen_i != 4'h0) || (axi_awsize_i != 3'b010); // error if write burst and more/less than 4B transfer
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assign rd_errorw = (axi_arlen_i != 4'h0) || (axi_arsize_i != 3'b010); // error if read burst and more/less than 4B transfer
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always @(posedge axi_clk_i) begin
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if (axi_rstn_i == 1'b0) begin
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rd_do <= 1'b0 ;
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rd_error <= 1'b0 ;
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end
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else begin
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if (axi_arvalid_i && !rd_do && !axi_awvalid_i && !wr_do) // accept just one read request - write has priority
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rd_do <= 1'b1 ;
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else if (axi_rready_i && rd_do && ack)
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rd_do <= 1'b0 ;
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if (axi_arvalid_i && axi_arready_o) begin // latch ID and address
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rd_arid <= axi_arid_i ;
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rd_araddr <= axi_araddr_i ;
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rd_error <= rd_errorw ;
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end
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end
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end
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always @(posedge axi_clk_i) begin
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if (axi_rstn_i == 1'b0) begin
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wr_do <= 1'b0 ;
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wr_error <= 1'b0 ;
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end
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else begin
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if (axi_awvalid_i && !wr_do && !rd_do) // accept just one write request - if idle
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wr_do <= 1'b1 ;
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else if (axi_bready_i && wr_do && ack)
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wr_do <= 1'b0 ;
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if (axi_awvalid_i && axi_awready_o) begin // latch ID and address
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wr_awid <= axi_awid_i ;
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wr_awaddr <= axi_awaddr_i ;
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wr_error <= wr_errorw ;
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end
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if (axi_wvalid_i && wr_do) begin // latch ID and write data
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wr_wid <= axi_wid_i ;
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wr_wdata <= axi_wdata_i ;
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end
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end
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end
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assign axi_awready_o = !wr_do && !rd_do ;
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assign axi_wready_o = (wr_do && axi_wvalid_i) || (wr_errorw && axi_wvalid_i) ;
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assign axi_bid_o = wr_awid ;
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//assign axi_bresp_o = {wr_error,1'b0} ; // 2'b10 SLVERR
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//assign axi_bvalid_o = (sys_wen_o && axi_bready_i) || (wr_error && axi_bready_i) ;
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assign axi_arready_o = !rd_do && !wr_do && !axi_awvalid_i ;
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assign axi_rid_o = rd_arid ;
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//assign axi_rdata_o = sys_rdata_i ;
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always @(posedge axi_clk_i) begin
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if (axi_rstn_i == 1'b0) begin
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axi_bvalid_o <= 1'b0 ;
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axi_bresp_o <= 2'h0 ;
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axi_rlast_o <= 1'b0 ;
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axi_rvalid_o <= 1'b0 ;
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axi_rresp_o <= 2'h0 ;
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end
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else begin
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axi_bvalid_o <= wr_do && ack ;
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axi_bresp_o <= {(wr_error || ack_cnt[5]),1'b0} ; // 2'b10 SLVERR 2'b00 OK
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axi_rlast_o <= rd_do && ack ;
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axi_rvalid_o <= rd_do && ack ;
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axi_rresp_o <= {(rd_error || ack_cnt[5]),1'b0} ; // 2'b10 SLVERR 2'b00 OK
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axi_rdata_o <= sys_rdata_i ;
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end
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end
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// acknowledge protection
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always @(posedge axi_clk_i) begin
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if (axi_rstn_i == 1'b0) begin
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ack_cnt <= 6'h0 ;
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end
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else begin
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if ((axi_arvalid_i && axi_arready_o) || (axi_awvalid_i && axi_awready_o)) // rd || wr request
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ack_cnt <= 6'h1 ;
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else if (ack)
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ack_cnt <= 6'h0 ;
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else if (|ack_cnt)
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ack_cnt <= ack_cnt + 6'h1 ;
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end
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end
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assign ack = sys_ack_i || ack_cnt[5] || (rd_do && rd_errorw) || (wr_do && wr_errorw); // bus acknowledge or timeout or error
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//------------------------------------------
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// Simple slave interface
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always @(posedge axi_clk_i) begin
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if (axi_rstn_i == 1'b0) begin
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sys_wen_o <= 1'b0 ;
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sys_ren_o <= 1'b0 ;
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sys_sel_o <= {AXI_SW{1'b0}} ;
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end
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else begin
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sys_wen_o <= wr_do && axi_wvalid_i && !wr_errorw ;
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sys_ren_o <= axi_arvalid_i && axi_arready_o && !rd_errorw ;
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sys_sel_o <= {AXI_SW{1'b1}} ;
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end
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end
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assign sys_addr_o = rd_do ? rd_araddr : wr_awaddr ;
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assign sys_wdata_o = wr_wdata ;
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endmodule
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