forked from M-Labs/nix-servo
194 lines
7.5 KiB
Python
194 lines
7.5 KiB
Python
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# This file is part of Fast Servo Software Package.
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#
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# Copyright (C) 2023 Jakub Matyas
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# Warsaw University of Technology <jakubk.m@gmail.com>
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <https://www.gnu.org/licenses/>.
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from migen import *
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class PS7(Module):
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def __init__(self, platform, ps7_name=None):
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self.frstn = Signal()
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self.ps7_tcl = []
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self.platform = platform
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self.ps7_name = "Zynq" if ps7_name is None else ps7_name
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ps7_clk = platform.request("ps7_clk")
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ps7_porb = platform.request("ps7_porb")
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ps7_srstb = platform.request("ps7_srstb")
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ps7_mio = platform.request("ps7_mio")
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ps7_ddram = platform.request("ps7_ddram")
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self.cpu_params = dict(
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# Clk / Rst.
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io_PS_CLK = ps7_clk,
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io_PS_PORB = ps7_porb,
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io_PS_SRSTB = ps7_srstb,
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# MIO.
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io_MIO = ps7_mio,
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# DDRAM.
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io_DDR_Addr = ps7_ddram.addr,
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io_DDR_BankAddr = ps7_ddram.ba,
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io_DDR_CAS_n = ps7_ddram.cas_n,
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io_DDR_Clk_n = ps7_ddram.ck_n,
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io_DDR_Clk = ps7_ddram.ck_p,
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io_DDR_CKE = ps7_ddram.cke,
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io_DDR_CS_n = ps7_ddram.cs_n,
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io_DDR_DM = ps7_ddram.dm,
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io_DDR_DQ = ps7_ddram.dq,
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io_DDR_DQS_n = ps7_ddram.dqs_n,
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io_DDR_DQS = ps7_ddram.dqs_p,
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io_DDR_ODT = ps7_ddram.odt,
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io_DDR_RAS_n = ps7_ddram.ras_n,
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io_DDR_DRSTB = ps7_ddram.reset_n,
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io_DDR_WEB = ps7_ddram.we_n,
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io_DDR_VRN = ps7_ddram.vrn,
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io_DDR_VRP = ps7_ddram.vrp,
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# USB0.
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# i_USB0_VBUS_PWRFAULT = 0,
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# Fabric Clk / Rst.
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# o_FCLK_CLK0 = ClockSignal("ps7"),
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o_FCLK_RESET0_N = self.frstn
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)
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self.set_ps7(name=self.ps7_name,
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config={
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**self.platform.ps7_config
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})
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def add_ps7_config(self, config):
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# Config must be provided as a config, value dict.
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assert isinstance(config, dict)
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# Add configs to PS7.
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self.ps7_tcl.append("set_property -dict [list \\")
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for config, value in config.items():
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self.ps7_tcl.append("CONFIG.{} {} \\".format(config, '{{' + str(value) + '}}'))
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self.ps7_tcl.append(f"] [get_ips {self.ps7_name}]")
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def set_ps7(self, name=None, config=None, preset=None):
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self.ps7_name = name
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self.ps7_tcl.append(f"set ps7 [create_ip -vendor xilinx.com -name processing_system7 -module_name {self.ps7_name}]")
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self.add_ps7_config(config)
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def add_axi_gp_master(self, interface):
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# assert type(interface) is Axi2Sys
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axi_interface = interface
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self.cpu_params.update({
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# AXI GP clk.
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f"i_M_AXI_GP0_ACLK" : axi_interface.aclk,
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# AXI GP aw.
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f"o_M_AXI_GP0_AWVALID" : axi_interface.awvalid,
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f"i_M_AXI_GP0_AWREADY" : axi_interface.awready,
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f"o_M_AXI_GP0_AWADDR" : axi_interface.awaddr,
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f"o_M_AXI_GP0_AWBURST" : axi_interface.awburst,
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f"o_M_AXI_GP0_AWLEN" : axi_interface.awlen,
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f"o_M_AXI_GP0_AWSIZE" : axi_interface.awsize,
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f"o_M_AXI_GP0_AWID" : axi_interface.awid,
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f"o_M_AXI_GP0_AWLOCK" : axi_interface.awlock,
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f"o_M_AXI_GP0_AWPROT" : axi_interface.awprot,
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f"o_M_AXI_GP0_AWCACHE" : axi_interface.awcache,
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f"o_M_AXI_GP0_AWQOS" : axi_interface.awqos,
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# AXI GP w.
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f"o_M_AXI_GP0_WVALID" : axi_interface.wvalid,
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f"o_M_AXI_GP0_WLAST" : axi_interface.wlast,
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f"i_M_AXI_GP0_WREADY" : axi_interface.wready,
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f"o_M_AXI_GP0_WID" : axi_interface.wid,
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f"o_M_AXI_GP0_WDATA" : axi_interface.wdata,
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f"o_M_AXI_GP0_WSTRB" : axi_interface.wstrb,
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# AXI GP b.
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f"i_M_AXI_GP0_BVALID" : axi_interface.bvalid,
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f"o_M_AXI_GP0_BREADY" : axi_interface.bready,
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f"i_M_AXI_GP0_BID" : axi_interface.bid,
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f"i_M_AXI_GP0_BRESP" : axi_interface.bresp,
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# AXI GP ar.
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f"o_M_AXI_GP0_ARVALID" : axi_interface.arvalid,
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f"i_M_AXI_GP0_ARREADY" : axi_interface.arready,
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f"o_M_AXI_GP0_ARADDR" : axi_interface.araddr,
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f"o_M_AXI_GP0_ARBURST" : axi_interface.arburst,
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f"o_M_AXI_GP0_ARLEN" : axi_interface.arlen,
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f"o_M_AXI_GP0_ARID" : axi_interface.arid,
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f"o_M_AXI_GP0_ARLOCK" : axi_interface.arlock,
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f"o_M_AXI_GP0_ARSIZE" : axi_interface.arsize,
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f"o_M_AXI_GP0_ARPROT" : axi_interface.arprot,
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f"o_M_AXI_GP0_ARCACHE" : axi_interface.arcache,
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f"o_M_AXI_GP0_ARQOS" : axi_interface.arqos,
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# AXI GP r.
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f"i_M_AXI_GP0_RVALID" : axi_interface.rvalid,
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f"o_M_AXI_GP0_RREADY" : axi_interface.rready,
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f"i_M_AXI_GP0_RLAST" : axi_interface.rlast,
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f"i_M_AXI_GP0_RID" : axi_interface.rid,
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f"i_M_AXI_GP0_RRESP" : axi_interface.rresp,
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f"i_M_AXI_GP0_RDATA" : axi_interface.rdata,
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})
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def add_i2c_emio(self, platform, i2c_name, i2c_number):
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ps7_i2c_pads = platform.request(i2c_name, i2c_number) #, loose=True)
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if ps7_i2c_pads is not None:
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o_i2c_scl = Signal()
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i_i2c_scl = Signal()
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t_i2c_scl = Signal()
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o_i2c_sda = Signal()
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i_i2c_sda = Signal()
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t_i2c_sda = Signal()
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self.specials += Instance("IOBUF",
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i_T = t_i2c_sda,
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i_I = o_i2c_sda,
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io_IO = ps7_i2c_pads.sda,
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o_O = i_i2c_sda,
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)
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self.specials += Instance("IOBUF",
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i_T = t_i2c_scl,
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i_I = o_i2c_scl,
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io_IO = ps7_i2c_pads.scl,
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o_O = i_i2c_scl,
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)
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self.cpu_params.update({
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f"i_I2C{i2c_number}_SCL_I" : i_i2c_scl,
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f"o_I2C{i2c_number}_SCL_T" : t_i2c_scl,
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f"o_I2C{i2c_number}_SCL_O" : o_i2c_scl,
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f"i_I2C{i2c_number}_SDA_I" : i_i2c_sda,
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f"o_I2C{i2c_number}_SDA_T" : t_i2c_sda,
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f"o_I2C{i2c_number}_SDA_O" : o_i2c_sda,
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})
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def do_finalize(self):
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if len(self.ps7_tcl):
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self.ps7_tcl += [
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f"upgrade_ip [get_ips {self.ps7_name}]",
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f"generate_target all [get_ips {self.ps7_name}]",
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f"synth_ip [get_ips {self.ps7_name}]"
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]
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self.platform.toolchain.pre_synthesis_commands += self.ps7_tcl
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self.specials += Instance(self.ps7_name, **self.cpu_params)
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