forked from M-Labs/zynq-rs
171 lines
4.6 KiB
Rust
171 lines
4.6 KiB
Rust
use r0::zero_bss;
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use core::ptr::write_volatile;
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use libregister::{
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VolatileCell,
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RegisterR, RegisterW, RegisterRW,
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};
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use libcortex_a9::{asm, l2c, regs::*, cache, mmu, spin_lock_yield, notify_spin_lock, enable_fpu};
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use libboard_zynq::{slcr, mpcore};
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extern "C" {
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static mut __bss_start: u32;
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static mut __bss_end: u32;
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static mut __stack0_start: u32;
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static mut __stack1_start: u32;
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fn main_core0();
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fn main_core1();
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}
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static mut CORE1_ENABLED: VolatileCell<bool> = VolatileCell::new(false);
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#[link_section = ".text.boot"]
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#[no_mangle]
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pub unsafe extern "C" fn Reset() -> ! {
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match MPIDR.read().cpu_id() {
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0 => {
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SP.write(&mut __stack0_start as *mut _ as u32);
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boot_core0();
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}
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1 => {
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while !CORE1_ENABLED.get() {
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spin_lock_yield();
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}
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SP.write(&mut __stack1_start as *mut _ as u32);
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boot_core1();
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}
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_ => unreachable!(),
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}
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}
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#[inline(never)]
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unsafe extern "C" fn boot_core0() -> ! {
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l1_cache_init();
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enable_fpu();
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let mpcore = mpcore::RegisterBlock::mpcore();
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mpcore.scu_invalidate.invalidate_all_cores();
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zero_bss(&mut __bss_start, &mut __bss_end);
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let mmu_table = mmu::L1Table::get()
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.setup_flat_layout();
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mmu::with_mmu(mmu_table, || {
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mpcore.scu_control.start();
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ACTLR.enable_smp();
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ACTLR.enable_prefetch();
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// TODO: Barriers reqd when core1 is not yet starting?
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asm::dmb();
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asm::dsb();
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asm::enable_irq();
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main_core0();
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panic!("return from main");
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});
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}
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#[inline(never)]
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unsafe extern "C" fn boot_core1() -> ! {
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l1_cache_init();
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let mpcore = mpcore::RegisterBlock::mpcore();
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mpcore.scu_invalidate.invalidate_core1();
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let mmu_table = mmu::L1Table::get();
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mmu::with_mmu(mmu_table, || {
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ACTLR.enable_smp();
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ACTLR.enable_prefetch();
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// TODO: Barriers reqd when core1 is not yet starting?
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asm::dmb();
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asm::dsb();
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asm::enable_irq();
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main_core1();
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panic!("return from main_core1");
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});
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}
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fn l1_cache_init() {
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use libcortex_a9::cache::*;
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// Invalidate TLBs
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tlbiall();
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// Invalidate I-Cache
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iciallu();
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// Invalidate Branch Predictor Array
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bpiall();
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// Invalidate D-Cache
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//
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// NOTE: It is both faster and correct to only invalidate instead
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// of also flush the cache (as was done before with
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// `dccisw()`) and it is correct to perform this operation
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// for all of the L1 data cache rather than a (previously
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// unspecified) combination of one cache set and one cache
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// way.
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dciall_l1();
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}
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pub struct Core1 {
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}
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impl Core1 {
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/// Reset and start core1
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pub fn start(sdram: bool) -> Self {
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// reset and stop (safe to repeat)
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_rst1(true));
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_clkstop1(true));
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_rst1(false));
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});
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if sdram {
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// Cores always start from OCM no matter what you do.
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// Make up a vector table there that just jumps to SDRAM.
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for i in 0..8 {
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unsafe {
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// this is the ARM instruction "b +0x00100000"
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write_volatile((i*4) as *mut u32, 0xea03fffe);
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}
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}
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}
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unsafe {
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CORE1_ENABLED.set(true);
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}
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// Flush cache-line
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cache::dcc(unsafe { &CORE1_ENABLED });
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if sdram {
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cache::dccmvac(0);
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asm::dsb();
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l2c::l2_cache_clean(0);
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l2c::l2_cache_sync();
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}
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// wake up core1
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_rst1(false));
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_clkstop1(false));
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});
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notify_spin_lock();
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Core1 {}
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}
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pub fn disable(&self) {
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unsafe {
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CORE1_ENABLED.set(false);
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cache::dccmvac(&CORE1_ENABLED as *const _ as usize);
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asm::dsb();
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}
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self.restart();
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}
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pub fn restart(&self) {
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_rst1(true));
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_clkstop1(true));
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_rst1(false));
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_clkstop1(false));
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});
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}
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}
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