515d3bb381
libboard_zynq: configure ddr while keeping rstb low
2020-11-08 22:47:59 +01:00
7e22010d7d
libboard_zynq: fix pll_cp/pll_res swap in ClockSource::setup()
2020-11-08 22:46:43 +01:00
9ee77d8f44
libboard_zynq: indent ps7_init/cora_z7_10
2020-11-08 19:32:31 +01:00
e508b78b3e
libboard_zynq: add ps7_init for cora_z7_10
2020-11-08 19:28:59 +01:00
f60d0589cc
fix ps7_init compilation error and warnings
2020-10-01 00:17:47 +08:00
c336e450b1
libboard_zynq/eth/phy: add PEF7071
2020-09-29 16:01:54 +08:00
6af453494b
libboard_zynq/ddr: use ps7_init for redpitaya ddr
2020-09-26 17:01:37 +08:00
e601ac9c45
remove flash support
...
PITA to get to work and most boards have SD.
2020-09-09 20:13:13 +08:00
a6955edf14
add Red Pitaya support (WIP)
2020-09-09 20:10:05 +08:00
c634313d5e
update authors in cargo.toml
2020-09-09 19:36:25 +08:00
ae244082ed
more cpu options
2020-09-07 16:13:51 +08:00
66c66447dd
fix some compilation warnings
2020-09-06 00:17:59 +08:00
a73df780d0
libboard_zynq/slcr: fixed boot mode pins value
...
Notice that the bits in the table in UG585 are out of order.
2020-08-31 12:35:11 +08:00
e73ec731aa
libboard_zynq/smoltcp: default without ipv6 support
...
SZL netboot binary size too large with ipv6.
We can enable the ipv6 support in the runtime crate instead.
2020-08-31 12:07:20 +08:00
273f9ea72b
libboard_zynq/eth: fix comment
2020-08-24 21:47:10 +08:00
671968bac3
libboard_zynq/eth: fixed tx lost packet
2020-08-24 15:51:01 +08:00
bb09d25378
libboard_zynq/ethernet: ethernet fix and config
2020-08-21 13:34:02 +08:00
b268fe015a
stdio::drop_uart(): add delay
2020-08-17 19:38:41 +02:00
1a96a7550a
libboard_zynq: make RegisterBlock constructors more consistent
2020-08-13 14:49:26 +08:00
36947104e3
libboard_zynq: make constructor names more consistent
2020-08-13 13:31:53 +08:00
11089d8a64
i2c: delete dead code
2020-08-12 16:51:25 +08:00
76a4cac873
i2c: disable its usage on Cora Z7-10
2020-08-10 14:24:13 +08:00
4614ed1371
i2c: simplify ctor_common()
2020-08-08 10:06:11 +08:00
16b2df91ca
i2c: fix GPIO register mapping, I2C control & EEPROM write operations
2020-08-07 11:10:18 +08:00
f7d3135ec7
i2c: implement EEPROM operations; add CountDown waiting indication
2020-08-05 20:10:30 +08:00
c60230af25
i2c: implement basic i2c bitbanging
2020-08-05 17:35:33 +08:00
a36a82d86d
reduce ethernet verbosity
2020-08-04 22:15:01 +08:00
2927c43309
libboard_zynq/gic: refactored and added SGI functions.
2020-08-03 12:35:17 +08:00
187801c4a7
gic: start implementation
2020-08-03 12:35:17 +08:00
91ece367f2
libboard_zynq/mpcore: added generated register definitions
2020-08-03 12:35:17 +08:00
1f05e6977e
eth::phy: replace ExtendedStatus with PSSR
2020-07-29 21:49:18 +02:00
e408a8b22d
eth::phy::extended_status: fix cap_1000base_x_full() bit position
2020-07-29 21:29:28 +02:00
27effb6257
eth::phy: s/Marvel/Marvell/
2020-07-29 20:08:38 +02:00
de5f605d60
eth: refactor peripheral instance into type parameter, improve clock setup
2020-07-29 19:45:01 +02:00
ef4fb598fb
ddr: improve dci divisors calculation
2020-07-28 00:43:33 +02:00
f36b1a610e
timer::global: wrap us in Microseconds, impl embedded_hal blocking delay traits
2020-07-22 23:41:15 +02:00
7f45d10af3
timer::global::CountDown: fix delaying from "up to" to "at least" the timespan
2020-07-22 22:43:10 +02:00
855d94c48e
dmac: remove unused module
2020-07-20 19:42:32 +02:00
f8785c3f07
fix some compilation warnings
2020-07-19 15:39:08 +08:00
484e385160
eth: implement DeviceCapabilities.max_burst_size
...
this is a hint that /could/ boost TCP performance.
2020-07-16 00:17:13 +02:00
371e59cef5
libboard_zynq: add fpgax_clk_ctrl registers
2020-07-07 19:37:51 +08:00
e4e7141bf3
ddr: delint
2020-07-06 19:46:18 +02:00
0c60d684e4
slcr: remove soft reset
...
Does not work and probably difficult to get to work.
2020-07-06 13:06:10 +08:00
21c0c5cbc8
Revert "simplify ps7_init"
...
What the simplified ps7_init does can now be reproduced by the DDRC driver.
On the other hand, we are still experiencing crazy Zynq instability issues, so keep the original ps7_init around for debugging.
This reverts commit 9fcf9243f2
2020-07-06 11:55:04 +08:00
90904634cd
DDR: fixed register write.
...
Previously it writes `0x20066`, while the ps7_init set it to be
`0x200066`, notice the 1 more 0.
This should perform the same writes to the registers, so we do not have
to apply the ps7_init in artiq_zynq.
2020-07-06 11:46:37 +08:00
ae4d3e2455
smoltcp: enable IPv6
2020-07-06 11:30:48 +08:00
9fcf9243f2
simplify ps7_init
2020-07-06 00:52:40 +08:00
f0697c3ec3
ddr: implement additional configuration
2020-07-03 02:20:10 +02:00
b2c707d543
ddr: remove superfluous _reg from register names
2020-07-03 02:20:10 +02:00
c0e66a632c
ps7_init: move from experiments to libboard_zynq
2020-06-25 01:40:42 +02:00
