23 Commits

Author	SHA1	Message	Date
Astro	1033648c3e	add l1_cache_init()	2019-05-23 19:05:06 +02:00
Astro	179c617904	add register_bits_typed! macro	2019-05-23 18:29:05 +02:00
Astro	785e726661	RegisterW/RegisterRW: required &mut self for safety	2019-05-23 18:01:18 +02:00
Astro	62ca26fa71	slcr: abstract with RegisterBlock	2019-05-23 17:52:06 +02:00
Astro	fd7fd0db14	main: rm unused feature #![feature(global_asm)]	2019-05-23 16:06:41 +02:00
Astro	ea62d4fdec	uart: make baudrate configurable, run at 115,200 baud	2019-05-23 15:50:53 +02:00
Astro	15883293ac	uart: use div_round_closest in baud_rate_gen	2019-05-23 15:37:07 +02:00
Astro	7428fec200	uart: add more channel_sts flags, wait for tx_fifo_empty() before sending	2019-05-23 15:36:34 +02:00
Astro	673d585d2f	uart: extend regs	2019-05-22 01:42:24 +02:00
Astro	b296fc1d7f	uart: add baud_rate_gen	2019-05-22 01:42:00 +02:00
Astro	43b6d3acd0	uart: wait for reset	2019-05-21 02:53:59 +02:00
Astro	47ec0116a9	use uart1 with more configuration	2019-05-21 01:30:54 +02:00
Astro	5d02fe5c95	slcr: with_slcr() for unlock/lock	2019-05-21 01:30:17 +02:00
Astro	351d18c10f	add register_at! macro	2019-05-20 23:01:50 +02:00
Astro	c88374eab1	fix SP init	2019-05-20 01:21:22 +02:00
Astro	b754581452	eth: add regs and init	2019-05-07 19:28:33 +02:00
Astro	7872e00182	uart: move logic outside regs	2019-05-07 17:46:37 +02:00
Astro	275f297309	uart: impl fmt::Write	2019-05-07 16:45:31 +02:00
Astro	ca9b10dce8	refactor regs macros for RO/WO/RW access	2019-05-07 00:32:45 +02:00
Astro	1e540a1175	replace #[repr(packed)] with #[repr(C)] ... avoids warnings regarding unsafe behaviour	2019-05-07 00:05:38 +02:00
Astro	fdc6c38de6	enable_uart0(): add srcsel	2019-05-07 00:01:43 +02:00
Astro	55957eea09	regs macros	2019-05-06 23:56:53 +02:00
Astro	9b414e2408	PoC: boot, uart output in qemu	2019-05-05 14:56:23 +02:00