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1033648c3e
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add l1_cache_init()
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2019-05-23 19:05:06 +02:00 |
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179c617904
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add register_bits_typed! macro
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2019-05-23 18:29:05 +02:00 |
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785e726661
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RegisterW/RegisterRW: required &mut self for safety
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2019-05-23 18:01:18 +02:00 |
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62ca26fa71
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slcr: abstract with RegisterBlock
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2019-05-23 17:52:06 +02:00 |
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fd7fd0db14
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main: rm unused feature #![feature(global_asm)]
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2019-05-23 16:06:41 +02:00 |
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ea62d4fdec
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uart: make baudrate configurable, run at 115,200 baud
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2019-05-23 15:50:53 +02:00 |
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15883293ac
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uart: use div_round_closest in baud_rate_gen
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2019-05-23 15:37:07 +02:00 |
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7428fec200
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uart: add more channel_sts flags, wait for tx_fifo_empty() before sending
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2019-05-23 15:36:34 +02:00 |
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673d585d2f
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uart: extend regs
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2019-05-22 01:42:24 +02:00 |
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b296fc1d7f
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uart: add baud_rate_gen
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2019-05-22 01:42:00 +02:00 |
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43b6d3acd0
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uart: wait for reset
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2019-05-21 02:53:59 +02:00 |
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47ec0116a9
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use uart1 with more configuration
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2019-05-21 01:30:54 +02:00 |
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5d02fe5c95
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slcr: with_slcr() for unlock/lock
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2019-05-21 01:30:17 +02:00 |
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351d18c10f
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add register_at! macro
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2019-05-20 23:01:50 +02:00 |
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c88374eab1
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fix SP init
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2019-05-20 01:21:22 +02:00 |
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b754581452
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eth: add regs and init
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2019-05-07 19:28:33 +02:00 |
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7872e00182
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uart: move logic outside regs
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2019-05-07 17:46:37 +02:00 |
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275f297309
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uart: impl fmt::Write
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2019-05-07 16:45:31 +02:00 |
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ca9b10dce8
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refactor regs macros for RO/WO/RW access
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2019-05-07 00:32:45 +02:00 |
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1e540a1175
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replace #[repr(packed)] with #[repr(C)]
avoids warnings regarding unsafe behaviour
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2019-05-07 00:05:38 +02:00 |
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fdc6c38de6
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enable_uart0(): add srcsel
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2019-05-07 00:01:43 +02:00 |
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55957eea09
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regs macros
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2019-05-06 23:56:53 +02:00 |
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9b414e2408
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PoC: boot, uart output in qemu
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2019-05-05 14:56:23 +02:00 |
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