forked from M-Labs/zynq-rs
zynq::slcr: doc, fix
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@ -247,6 +247,8 @@ pub struct RegisterBlock {
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register_at!(RegisterBlock, 0xF8000000, new);
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impl RegisterBlock {
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/// Required to modify these sclr registers: scl, pss_rst_ctrl,
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/// apu_ctrl, and wdt_clk_sel
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pub fn unlocked<F: FnMut(&mut Self) -> R, R>(mut f: F) -> R {
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let mut self_ = Self::new();
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self_.slcr_unlock.unlock();
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@ -287,7 +289,7 @@ impl SlcrUnlock {
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}
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register!(pll_ctrl, PllCtrl, RW, u32);
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register_bits!(pll_ctrl, pll_fdiv, u8, 12, 18);
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register_bits!(pll_ctrl, pll_fdiv, u16, 12, 18);
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register_bit!(pll_ctrl, pll_bypass_force, 4);
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register_bit!(pll_ctrl, pll_bypass_qual, 3);
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register_bit!(pll_ctrl, pll_pwrdwn, 1);
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