forked from M-Labs/zynq-rs
libboard_zynq: add ps7_init for cora_z7_10
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aef010cb14
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@ -145,6 +145,8 @@ pub fn main_core0() {
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let timer = libboard_zynq::timer::GlobalTimer::start();
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let mut ddr = zynq::ddr::DdrRam::ddrram();
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// ddr init may call ps7_init, reconfiguring the uart
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libboard_zynq::stdio::drop_uart();
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#[cfg(not(feature = "target_zc706"))]
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ddr.memtest();
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ram::init_alloc_ddr(&mut ddr);
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@ -4,7 +4,7 @@ use crate::{print, println};
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use super::slcr::{self, DdriobVrefSel};
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use super::clocks::{Clocks, source::{DdrPll, ClockSource}};
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#[cfg(feature = "target_redpitaya")]
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#[cfg(any(feature = "target_redpitaya", feature = "target_cora_z7_10"))]
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use super::ps7_init;
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mod regs;
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@ -30,11 +30,11 @@ pub struct DdrRam {
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impl DdrRam {
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pub fn ddrram() -> Self {
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if cfg!(feature = "target_redpitaya") {
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if cfg!(any(feature = "target_redpitaya", feature = "target_cora_z7_10")) {
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// We have not yet fixed red pitaya initialization yet. It seems
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// that the clock configuration, iob settings and ddr settings are
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// all problematic
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#[cfg(feature = "target_redpitaya")]
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#[cfg(any(feature = "target_redpitaya", feature = "target_cora_z7_10"))]
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ps7_init::apply();
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let regs = regs::RegisterBlock::ddrc();
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DdrRam { regs }
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File diff suppressed because it is too large
Load Diff
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@ -5,14 +5,18 @@ use crate::println;
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mod zc706;
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#[cfg(feature = "target_redpitaya")]
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mod redpitaya;
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#[cfg(not(any(feature = "target_zc706", feature = "target_redpitaya")))]
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#[cfg(feature = "target_cora_z7_10")]
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mod cora_z7_10;
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#[cfg(not(any(feature = "target_zc706", feature = "target_redpitaya", feature = "target_cora_z7_10")))]
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mod none;
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#[cfg(feature = "target_zc706")]
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use zc706 as target;
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#[cfg(feature = "target_redpitaya")]
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use redpitaya as target;
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#[cfg(not(any(feature = "target_zc706", feature = "target_redpitaya")))]
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#[cfg(feature = "target_cora_z7_10")]
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use cora_z7_10 as target;
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#[cfg(not(any(feature = "target_zc706", feature = "target_redpitaya", feature = "target_cora_z7_10")))]
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use none as target;
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pub fn report_differences() {
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