forked from M-Labs/zynq-rs
main: add UART_RATE
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@ -73,8 +73,10 @@ fn l1_cache_init() {
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asm::isb();
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asm::isb();
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}
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}
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const UART_RATE: u32 = 115_200;
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fn main() {
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fn main() {
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let mut uart = Uart::serial(115_200);
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let mut uart = Uart::serial(UART_RATE);
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loop {
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loop {
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for i in 0.. {
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for i in 0.. {
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writeln!(uart, "i={}\r", i);
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writeln!(uart, "i={}\r", i);
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