forked from M-Labs/zynq-rs
uart: remove type conversion from baud_rate_gen
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a645d13f4b
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b961526b97
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@ -1,8 +1,8 @@
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use crate::regs::*;
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use crate::regs::*;
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use super::regs::{RegisterBlock, BaudRateGen, BaudRateDiv};
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use super::regs::{RegisterBlock, BaudRateGen, BaudRateDiv};
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const BDIV_MIN: u8 = 4;
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const BDIV_MIN: u32 = 4;
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const BDIV_MAX: u8 = 255;
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const BDIV_MAX: u32 = 255;
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const CD_MAX: u16 = 65535;
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const CD_MAX: u16 = 65535;
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fn div_round_closest(q: u32, d: u32) -> u32 {
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fn div_round_closest(q: u32, d: u32) -> u32 {
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@ -17,7 +17,6 @@ pub fn configure(regs: &mut RegisterBlock, mut clk: u32, baud: u32) {
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let mut best = None;
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let mut best = None;
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for bdiv in BDIV_MIN..=BDIV_MAX {
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for bdiv in BDIV_MIN..=BDIV_MAX {
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let bdiv: u32 = bdiv.into();
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let cd = div_round_closest(clk, baud * (bdiv + 1));
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let cd = div_round_closest(clk, baud * (bdiv + 1));
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if cd < 1 || cd > CD_MAX.into() {
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if cd < 1 || cd > CD_MAX.into() {
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continue;
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continue;
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