forked from M-Labs/zynq-rs
eth: begin phy communication
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5b15bb5c0a
commit
b13bf72c17
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@ -1,6 +1,7 @@
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use crate::regs::*;
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use crate::regs::*;
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use crate::slcr;
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use crate::slcr;
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pub mod phy;
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mod regs;
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mod regs;
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pub struct Eth {
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pub struct Eth {
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@ -13,6 +14,7 @@ impl Eth {
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// MDIO
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// MDIO
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slcr.mio_pin_53.write(
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slcr.mio_pin_53.write(
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slcr::MioPin53::zeroed()
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slcr::MioPin53::zeroed()
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.tri_enable(true)
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.l3_sel(0b100)
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.l3_sel(0b100)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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.pullup(true)
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@ -20,7 +22,6 @@ impl Eth {
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// MDC
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// MDC
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slcr.mio_pin_52.write(
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slcr.mio_pin_52.write(
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slcr::MioPin52::zeroed()
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slcr::MioPin52::zeroed()
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.tri_enable(true)
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.l3_sel(0b100)
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.l3_sel(0b100)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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.pullup(true)
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@ -220,5 +221,54 @@ impl Eth {
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.copy_all(true)
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.copy_all(true)
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.mdc_clk_div(0b111)
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.mdc_clk_div(0b111)
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);
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);
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// TODO: mac addr
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// TODO: Program the DMA Configuration register (gem.dma_cfg).
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self.regs.net_ctrl.write(
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regs::NetCtrl::zeroed()
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.mgmt_port_en(true)
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.tx_en(true)
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.rx_en(true)
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);
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}
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fn wait_phy_idle(&self) {
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let mut timeout = 5_000_000;
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while !self.regs.net_status.read().phy_mgmt_idle() {
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timeout -= 1;
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if timeout == 0 {
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break
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}
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}
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}
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}
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impl phy::PhyAccess for Eth {
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fn read_phy(&mut self, addr: u8, reg: u8) -> u16 {
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self.wait_phy_idle();
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self.regs.phy_maint.write(
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regs::PhyMaint::zeroed()
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.clause_22(true)
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.operation(regs::PhyOperation::Read)
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.phy_addr(addr)
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.reg_addr(reg)
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.must_10(0b10)
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);
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self.wait_phy_idle();
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self.regs.phy_maint.read().data()
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}
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fn write_phy(&mut self, addr: u8, reg: u8, data: u16) {
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self.wait_phy_idle();
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self.regs.phy_maint.write(
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regs::PhyMaint::zeroed()
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.clause_22(true)
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.operation(regs::PhyOperation::Write)
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.phy_addr(addr)
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.reg_addr(reg)
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.must_10(0b10)
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.data(data)
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);
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self.wait_phy_idle();
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}
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}
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}
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}
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@ -0,0 +1,8 @@
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pub trait PhyAccess {
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fn read_phy(&mut self, addr: u8, reg: u8) -> u16;
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fn write_phy(&mut self, addr: u8, reg: u8, data: u16);
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}
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pub trait PhyDevice {
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fn init() -> Self;
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}
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@ -124,7 +124,22 @@ impl RegisterBlock {
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}
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}
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register!(net_ctrl, NetCtrl, RW, u32);
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register!(net_ctrl, NetCtrl, RW, u32);
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register_bit!(net_ctrl, loopback_local, 1);
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register_bit!(net_ctrl, rx_en, 2);
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register_bit!(net_ctrl, tx_en, 3);
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register_bit!(net_ctrl, mgmt_port_en, 4);
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register_bit!(net_ctrl, clear_stat_regs, 5);
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register_bit!(net_ctrl, clear_stat_regs, 5);
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register_bit!(net_ctrl, incr_stat_regs, 6);
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register_bit!(net_ctrl, wren_stat_regs, 7);
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register_bit!(net_ctrl, back_pressure, 8);
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register_bit!(net_ctrl, start_tx, 9);
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register_bit!(net_ctrl, tx_halt, 10);
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register_bit!(net_ctrl, tx_pause_frame, 11);
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register_bit!(net_ctrl, tx_zeroq_pause_frame, 12);
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register_bit!(net_ctrl, str_rx_timestamp, 15);
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register_bit!(net_ctrl, en_pfc_pri_pause_rx, 16);
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register_bit!(net_ctrl, tx_pfc_pri_pri_pause_frame, 17);
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register_bit!(net_ctrl, flush_next_rx_dpram_pkt, 18);
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register!(net_cfg, NetCfg, RW, u32);
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register!(net_cfg, NetCfg, RW, u32);
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register_bit!(net_cfg,
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register_bit!(net_cfg,
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