forked from M-Labs/zynq-rs
cortex_a9::mmu: make OCM region cachable
This commit is contained in:
parent
1ba587ccf9
commit
a8cb085a25
|
@ -124,7 +124,7 @@ impl L1Table {
|
|||
tex: 0b101,
|
||||
domain: 0b1111,
|
||||
exec: true,
|
||||
cacheable: false,
|
||||
cacheable: true,
|
||||
bufferable: true,
|
||||
});
|
||||
/* (DDR cacheable) */
|
||||
|
|
Loading…
Reference in New Issue