forked from M-Labs/zynq-rs
zynq::flash: add more setup
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3180f1c3f7
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@ -6,7 +6,11 @@ use super::clocks::CpuClocks;
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pub mod regs;
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const FLASH_BAUD_RATE: u32 = 50_000_000;
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/// Flash Interface Driver
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///
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/// For 2x Spansion S25FL128SAGMFIR01
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pub struct Flash {
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regs: &'static mut regs::RegisterBlock,
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}
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@ -19,7 +23,8 @@ impl Flash {
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let regs = regs::RegisterBlock::qspi();
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let mut flash = Flash { regs };
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flash.configure();
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flash.configure((FLASH_BAUD_RATE - 1 + clock) / FLASH_BAUD_RATE);
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flash.setup_linear_addressing_mode();
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flash
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}
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@ -39,7 +44,46 @@ impl Flash {
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}
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fn setup_signals() {
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// TODO
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slcr::RegisterBlock::unlocked(|slcr| {
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// 1. Configure MIO pin 1 for chip select 0 output.
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slcr.mio_pin_01.write(
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slcr::MioPin01::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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);
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// Configure MIO pins 2 through 5 for I/O.
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slcr.mio_pin_02.write(
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slcr::MioPin02::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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);
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slcr.mio_pin_03.write(
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slcr::MioPin03::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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);
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slcr.mio_pin_04.write(
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slcr::MioPin04::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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);
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slcr.mio_pin_05.write(
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slcr::MioPin05::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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);
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// 3. Configure MIO pin 6 for serial clock 0 output.
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slcr.mio_pin_06.write(
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slcr::MioPin06::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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);
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// TODO: optional 2nd chip setup
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});
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}
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fn reset() {
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@ -55,13 +99,33 @@ impl Flash {
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});
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}
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fn configure(&mut self) {
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fn configure(&mut self, divider: u32) {
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// for a baud_rate_div=1 LPBK_DLY_ADJ would be required
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let mut baud_rate_div = 2u32;
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while baud_rate_div < 7 && 2u32.pow(1 + baud_rate_div) < divider {
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baud_rate_div += 1;
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}
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self.regs.config.modify(|_, w| w
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.baud_rate_div(4 /* TODO */)
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.baud_rate_div(baud_rate_div as u8)
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.mode_sel(true)
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.leg_flsh(true)
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.endian(false)
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.fifo_width(0b11)
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);
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}
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fn setup_linear_addressing_mode(&mut self) {
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self.regs.lqspi_cfg.modify(|_, w| w
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.inst_code(0x3)
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.u_page(false)
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.sep_bus(false)
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.two_mem(false)
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.lq_mode(true)
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);
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}
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pub fn ptr<T>(&mut self) -> *mut T {
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0xFC00_0000 as *mut _
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}
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}
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@ -1,6 +1,6 @@
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use volatile_register::{RO, WO, RW};
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use crate::{register, register_bit, register_bits, register_bits_typed};
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use crate::{register, register_bit, register_bits};
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#[repr(C)]
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pub struct RegisterBlock {
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@ -24,7 +24,7 @@ pub struct RegisterBlock {
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pub txd2: WO<u32>,
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pub txd3: WO<u32>,
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pub _unused3: [RO<u32>; 5],
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pub lqspi_cfg: RW<u32>,
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pub lqspi_cfg: LqspiCfg,
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pub lqspi_sts: RW<u32>,
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pub _unused4: [RO<u32>; 21],
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pub mod_id: RW<u32>,
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@ -49,7 +49,7 @@ register_bit!(config,
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/// Clock phase
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clk_ph, 2);
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register_bits!(config,
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/// divisor = 2 ** (1 + baud_rate_div)
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/// divider = 2 ** (1 + baud_rate_div)
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baud_rate_div, u8, 3, 5);
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register_bits!(config,
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/// Must be set to 0b11
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@ -76,3 +76,14 @@ register_bit!(config,
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register_bit!(config,
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/// false: legacy SPI mode, true: Flash memory interface mode
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leg_flsh, 31);
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register!(lqspi_cfg, LqspiCfg, RW, u32);
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register_bits!(lqspi_cfg, inst_code, u8, 0, 7);
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register_bits!(lqspi_cfg, dummy_byte, u8, 8, 10);
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register_bits!(lqspi_cfg, mode_bits, u8, 16, 23);
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register_bit!(lqspi_cfg, mode_on, 24);
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register_bit!(lqspi_cfg, mode_en, 25);
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register_bit!(lqspi_cfg, u_page, 28);
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register_bit!(lqspi_cfg, sep_bus, 29);
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register_bit!(lqspi_cfg, two_mem, 30);
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register_bit!(lqspi_cfg, lq_mode, 31);
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