forked from M-Labs/zynq-rs
libboard_zynq: use log logging
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619ebf147c
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@ -44,7 +44,7 @@ pub fn main_core0() {
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#[cfg(feature = "target_cora_z7_10")]
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const CPU_FREQ: u32 = 650_000_000;
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println!("Setup clock sources...");
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info!("Setup clock sources...");
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ArmPll::setup(2 * CPU_FREQ);
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Clocks::set_cpu_freq(CPU_FREQ);
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#[cfg(feature = "target_zc706")]
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@ -52,9 +52,9 @@ pub fn main_core0() {
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IoPll::setup(1_000_000_000);
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libboard_zynq::stdio::drop_uart();
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}
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println!("PLLs set up");
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info!("PLLs set up");
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let clocks = zynq::clocks::Clocks::get();
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println!("CPU Clocks: {}/{}/{}/{}", clocks.cpu_6x4x(), clocks.cpu_3x2x(), clocks.cpu_2x(), clocks.cpu_1x());
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info!("CPU Clocks: {}/{}/{}/{}", clocks.cpu_6x4x(), clocks.cpu_3x2x(), clocks.cpu_2x(), clocks.cpu_1x());
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let mut flash = zynq::flash::Flash::new(200_000_000).linear_addressing_mode();
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let flash_ram: &[u8] = unsafe { core::slice::from_raw_parts(flash.ptr(), flash.size()) };
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@ -223,7 +223,7 @@ pub fn main_core0() {
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let timestamp = timer.get_us();
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let seconds = timestamp / 1_000_000;
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let micros = timestamp % 1_000_000;
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println!("time: {:6}.{:06}s", seconds, micros);
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info!("time: {:6}.{:06}s", seconds, micros);
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}
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});
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@ -1,3 +1,4 @@
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use log::debug;
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use libregister::{RegisterR, RegisterW, RegisterRW};
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use super::slcr;
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@ -48,6 +49,8 @@ pub trait ClockSource {
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u32::from(pll_ctrl.read().pll_fdiv()) * PS_CLK
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}
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fn name() -> &'static str;
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/// Zynq-7000 AP SoC Technical Reference Manual:
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/// 25.10.4 PLLs
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fn setup(target_freq: u32) {
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@ -58,6 +61,7 @@ pub trait ClockSource {
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.expect("PLL_FDIV_LOCK_PARAM")
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.1.clone();
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debug!("Set {} to {} Hz", Self::name(), target_freq);
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slcr::RegisterBlock::unlocked(|slcr| {
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let (pll_ctrl, pll_cfg, pll_status) = Self::pll_regs(slcr);
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@ -108,6 +112,10 @@ impl ClockSource for ArmPll {
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fn pll_locked(pll_status: &mut crate::slcr::PllStatus) -> bool {
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pll_status.read().arm_pll_lock()
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}
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fn name() -> &'static str {
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&"ARM_PLL"
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}
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}
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/// DDR PLL: Recommended clock for the DDR DRAM controller and AXI_HP interfaces
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@ -130,6 +138,10 @@ impl ClockSource for DdrPll {
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fn pll_locked(pll_status: &mut crate::slcr::PllStatus) -> bool {
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pll_status.read().ddr_pll_lock()
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}
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fn name() -> &'static str {
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&"DDR_PLL"
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}
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}
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/// I/O PLL: Recommended clock for I/O peripherals
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@ -153,4 +165,8 @@ impl ClockSource for IoPll {
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fn pll_locked(pll_status: &mut crate::slcr::PllStatus) -> bool {
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pll_status.read().io_pll_lock()
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}
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fn name() -> &'static str {
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&"IO_PLL"
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}
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}
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@ -1,4 +1,5 @@
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use libregister::{RegisterR, RegisterW, RegisterRW};
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use log::{error, info};
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use crate::{print, println};
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use super::slcr::{self, DdriobVrefSel};
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use super::clocks::{Clocks, source::{DdrPll, ClockSource}};
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@ -38,11 +39,9 @@ impl DdrRam {
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DdrPll::setup(2 * DDR_FREQ);
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let clocks = Clocks::get();
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println!("Clocks: {:?}", clocks);
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let ddr3x_clk_divisor = 2;
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let ddr2x_clk_divisor = 3;
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println!("DDR 3x/2x clocks: {}/{}", clocks.ddr / u32::from(ddr3x_clk_divisor), clocks.ddr / u32::from(ddr2x_clk_divisor));
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info!("DDR 3x/2x clocks: {}/{}", clocks.ddr / u32::from(ddr3x_clk_divisor), clocks.ddr / u32::from(ddr2x_clk_divisor));
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.ddr_clk_ctrl.write(
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@ -63,7 +62,7 @@ impl DdrRam {
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.max(1).min(63) as u8;
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let divisor1 = ((DCI_FREQ - 1 + clocks.ddr) / DCI_FREQ / u32::from(divisor0))
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.max(1).min(63) as u8;
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println!("DDR DCI clock: {} Hz", clocks.ddr / u32::from(divisor0) / u32::from(divisor1));
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info!("DDR DCI clock: {} Hz", clocks.ddr / u32::from(divisor0) / u32::from(divisor1));
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slcr::RegisterBlock::unlocked(|slcr| {
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// Step 1.
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@ -226,7 +225,7 @@ impl DdrRam {
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let patterns: &'static [u32] = &[0xffff_ffff, 0x5555_5555, 0xaaaa_aaaa, 0];
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let mut expected = None;
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for (i, pattern) in patterns.iter().enumerate() {
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println!("memtest phase {} (status: {:?})", i, self.status());
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info!("memtest phase {} (status: {:?})", i, self.status());
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for megabyte in 0..=(slice.len() / (1024 * 1024)) {
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let start = megabyte * 1024 * 1024 / 4;
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@ -235,7 +234,7 @@ impl DdrRam {
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expected.map(|expected| {
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let read: u32 = *b;
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if read != expected {
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println!("{:08X}: expected {:08X}, read {:08X}", b as *mut _ as usize, expected, read);
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error!("{:08X}: expected {:08X}, read {:08X}", b as *mut _ as usize, expected, read);
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}
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});
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*b = *pattern;
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@ -1,6 +1,6 @@
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use core::ops::{Deref, DerefMut};
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use log::{error, info, warn};
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use libregister::*;
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use crate::println;
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use super::slcr;
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use super::clocks::Clocks;
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@ -389,7 +389,7 @@ impl<'r, 'rx, 'tx: 'a, 'a> smoltcp::phy::Device<'a> for &mut Eth<'r, rx::DescLis
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None
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}
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Err(e) => {
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println!("eth recv error: {:?}", e);
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error!("eth recv error: {:?}", e);
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None
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}
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}
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@ -555,7 +555,7 @@ impl<'r> EthInner<'r> {
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if self.link != link {
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match &link {
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Some(link) => {
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println!("eth: got {:?}", link);
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info!("eth: got {:?}", link);
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use phy::LinkSpeed::*;
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let txclock = match link.speed {
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@ -573,7 +573,7 @@ impl<'r> EthInner<'r> {
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);
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}
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None => {
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println!("eth: link lost");
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warn!("eth: link lost");
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phy.modify_control(self, |control|
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control.set_autoneg_enable(true)
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.set_restart_autoneg(true)
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@ -1,8 +1,9 @@
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//! Quad-SPI Flash Controller
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use crate::{print, println};
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use core::marker::PhantomData;
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use log::{error, info, warn};
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use libregister::{RegisterR, RegisterW, RegisterRW};
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use crate::{print, println};
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use super::slcr;
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use super::clocks::source::{IoPll, ClockSource};
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@ -422,17 +423,17 @@ impl Flash<Manual> {
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let sr1 = self.wait_while_sr1_zeroed();
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if sr1.e_err() {
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println!("E_ERR");
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error!("E_ERR");
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} else if sr1.p_err() {
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println!("P_ERR");
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error!("P_ERR");
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} else if sr1.wip() {
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print!("Erase in progress");
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info!("Erase in progress");
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while self.read_reg::<SR1>().wip() {
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print!(".");
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}
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println!("");
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} else {
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println!("erased? sr1={:02X}", sr1.inner);
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warn!("erased? sr1={:02X}", sr1.inner);
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}
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}
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@ -448,17 +449,17 @@ impl Flash<Manual> {
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let sr1 = self.read_reg::<SR1>();
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if sr1.e_err() {
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println!("E_ERR");
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error!("E_ERR");
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} else if sr1.p_err() {
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println!("P_ERR");
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error!("P_ERR");
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} else if sr1.wip() {
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println!("Program in progress");
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info!("Program in progress");
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while self.read_reg::<SR1>().wip() {
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print!(".");
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}
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println!("");
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} else {
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println!("programmed? sr1={:02X}", sr1.inner);
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warn!("programmed? sr1={:02X}", sr1.inner);
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}
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}
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