forked from M-Labs/zynq-rs
cortex_a9 regs: allow defining bit fields
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parent
1e16beb707
commit
69b65b5f72
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@ -1,32 +1,63 @@
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use crate::regs::{RegisterR, RegisterW};
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use crate::register_bit;
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use crate::regs::{RegisterR, RegisterW, RegisterRW};
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macro_rules! def_reg_get {
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macro_rules! def_reg_r {
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($name:tt, $type: ty, $asm_instr:tt) => {
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($name:tt, $type: ty, $asm_instr:tt) => {
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impl RegisterR for $name {
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impl RegisterR for $name {
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type R = $type;
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type R = $type;
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#[inline(always)]
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#[inline(always)]
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fn read(&self) -> Self::R {
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fn read(&self) -> Self::R {
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let mut value;
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let mut value: u32;
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unsafe { asm!($asm_instr : "=r" (value) ::: "volatile") }
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unsafe { asm!($asm_instr : "=r" (value) ::: "volatile") }
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value
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value.into()
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}
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}
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}
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}
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}
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}
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}
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}
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macro_rules! def_reg_set {
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macro_rules! def_reg_w {
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($name:ty, $type:ty, $asm_instr:tt) => {
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($name:ty, $type:ty, $asm_instr:tt) => {
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impl RegisterW for $name {
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impl RegisterW for $name {
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type W = $type;
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type W = $type;
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#[inline(always)]
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#[inline(always)]
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fn write(&mut self, value: Self::W) {
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fn write(&mut self, value: Self::W) {
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let value: u32 = value.into();
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unsafe { asm!($asm_instr :: "r" (value) :: "volatile") }
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unsafe { asm!($asm_instr :: "r" (value) :: "volatile") }
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}
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}
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fn zeroed() -> Self::W {
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fn zeroed() -> Self::W {
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0
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0u32.into()
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}
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}
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}
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}
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macro_rules! wrap_reg {
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($mod_name: ident) => {
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pub mod $mod_name {
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pub struct Read {
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pub inner: u32,
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}
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impl From<u32> for Read {
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fn from(value: u32) -> Self {
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Read { inner: value }
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}
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}
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pub struct Write {
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pub inner: u32,
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}
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impl From<u32> for Write {
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fn from(value: u32) -> Self {
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Write { inner: value }
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}
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}
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impl Into<u32> for Write {
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fn into(self) -> u32 {
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self.inner
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}
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}
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}
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}
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}
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}
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}
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@ -34,26 +65,55 @@ macro_rules! def_reg_set {
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/// Stack Pointer
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/// Stack Pointer
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pub struct SP;
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pub struct SP;
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def_reg_get!(SP, u32, "mov $0, sp");
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def_reg_r!(SP, u32, "mov $0, sp");
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def_reg_set!(SP, u32, "mov sp, $0");
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def_reg_w!(SP, u32, "mov sp, $0");
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/// Link register (function call return address)
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/// Link register (function call return address)
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pub struct LR;
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pub struct LR;
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def_reg_get!(LR, u32, "mov $0, lr");
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def_reg_r!(LR, u32, "mov $0, lr");
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def_reg_set!(LR, u32, "mov lr, $0");
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def_reg_w!(LR, u32, "mov lr, $0");
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pub struct MPIDR;
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pub struct MPIDR;
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def_reg_get!(MPIDR, u32, "mrc p15, 0, $0, c0, c0, 5");
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def_reg_r!(MPIDR, u32, "mrc p15, 0, $0, c0, c0, 5");
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pub struct DFAR;
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pub struct DFAR;
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def_reg_get!(DFAR, u32, "mrc p15, 0, $0, c6, c0, 0");
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def_reg_r!(DFAR, u32, "mrc p15, 0, $0, c6, c0, 0");
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pub struct DFSR;
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pub struct DFSR;
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def_reg_get!(DFSR, u32, "mrc p15, 0, $0, c5, c0, 0");
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def_reg_r!(DFSR, u32, "mrc p15, 0, $0, c5, c0, 0");
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pub struct SCTLR;
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pub struct SCTLR;
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def_reg_get!(SCTLR, u32, "mrc p15, 0, $0, c1, c0, 0");
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wrap_reg!(sctlr);
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def_reg_set!(SCTLR, u32, "mcr p15, 0, $0, c1, c0, 0");
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def_reg_r!(SCTLR, sctlr::Read, "mrc p15, 0, $0, c1, c0, 0");
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def_reg_w!(SCTLR, sctlr::Write, "mcr p15, 0, $0, c1, c0, 0");
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register_bit!(sctlr,
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/// Enables MMU
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m, 0);
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register_bit!(sctlr,
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/// Strict Alignment Checking
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a, 1);
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register_bit!(sctlr,
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/// Data Caching
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c, 2);
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register_bit!(sctlr, sw, 10);
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register_bit!(sctlr, z, 11);
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register_bit!(sctlr, i, 12);
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register_bit!(sctlr, v, 13);
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register_bit!(sctlr, ha, 17);
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register_bit!(sctlr, ee, 25);
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register_bit!(sctlr,
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/// (read-only)
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nmfi, 27);
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register_bit!(sctlr, unaligned, 22);
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register_bit!(sctlr,
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/// TEX Remap Enable
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tre, 28);
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register_bit!(sctlr,
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/// Access Flag Enable
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afe, 29);
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register_bit!(sctlr,
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/// Thumb Exception Enable
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te, 30);
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/// Invalidate TLBs
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/// Invalidate TLBs
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#[inline(always)]
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#[inline(always)]
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@ -68,7 +68,14 @@ fn l1_cache_init() {
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// (Initialize MMU)
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// (Initialize MMU)
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// Enable I-Cache and D-Cache
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// Enable I-Cache and D-Cache
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SCTLR.write(0x00401004);
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SCTLR.write(
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SCTLR::zeroed()
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.m(false)
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.a(false)
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.c(true)
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.i(true)
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.unaligned(true)
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);
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// Synchronization barriers
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// Synchronization barriers
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// Allows MMU to start
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// Allows MMU to start
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