forked from M-Labs/zynq-rs
add some fpga regs
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774e4e88a9
commit
29bf29a037
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@ -1,4 +1,5 @@
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use libregister::*;
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use crate::slcr;
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mod regs;
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pub struct DevC {
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@ -24,4 +25,16 @@ impl DevC {
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.pcap_pr(false)
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})
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}
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pub fn program(&mut self) {
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.init_preload_fpga();
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});
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while !self.regs.int_sts.read().ixr_pcfg_done() {}
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.init_postload_fpga();
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});
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}
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}
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@ -50,13 +50,20 @@ pub enum DdriobOutputEn {
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#[repr(u8)]
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pub enum DdriobVrefSel {
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/// For LPDDR2 with 1.2V IO
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Vref0_6V,
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Vref0_6V = 0b0001,
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/// For DDR3L with 1.35V IO
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Vref0_675V,
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Vref0_675V = 0b0010,
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/// For DDR3 with 1.5V IO
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Vref0_75V,
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Vref0_75V = 0b0100,
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/// For DDR2 with 1.8V IO
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Vref0_9V,
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Vref0_9V = 0b1000,
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}
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#[repr(u8)]
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pub enum LevelShifterEnable {
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DisableAll = 0x0,
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EnablePsToPl = 0xA,
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EnableAll = 0xF,
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}
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@ -130,7 +137,7 @@ pub struct RegisterBlock {
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pub smc_rst_ctrl: RW<u32>,
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pub ocm_rst_ctrl: RW<u32>,
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reserved4: [u32; 1],
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pub fpga_rst_ctrl: RW<u32>,
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pub fpga_rst_ctrl: FpgaRstCtrl,
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pub a9_cpu_rst_ctrl: A9CpuRstCtrl,
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reserved5: [u32; 1],
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pub rs_awdt_ctrl: RW<u32>,
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@ -219,7 +226,7 @@ pub struct RegisterBlock {
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pub sd0_wp_cd_sel: RW<u32>,
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pub sd1_wp_cd_sel: RW<u32>,
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reserved17: [u32; 50],
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pub lvl_shftr_en: RW<u32>,
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pub lvl_shftr_en: LvlShftr,
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reserved18: [u32; 3],
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pub ocm_cfg: RW<u32>,
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reserved19: [u32; 123],
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@ -265,6 +272,38 @@ impl RegisterBlock {
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.soft_rst(true)
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);
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}
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pub fn init_preload_fpga(&mut self) {
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// Assert FPGA top level output resets
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self.fpga_rst_ctrl.write(
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FpgaRstCtrl::zeroed()
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.fpga0_out_rst(true)
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.fpga1_out_rst(true)
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.fpga2_out_rst(true)
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.fpga3_out_rst(true)
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);
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// Disable level shifters
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self.lvl_shftr_en.write(
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LvlShftr::zeroed()
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);
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// Enable output level shifters
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self.lvl_shftr_en.write(
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LvlShftr::zeroed()
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.user_lvl_shftr_en(LevelShifterEnable::EnablePsToPl)
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);
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}
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pub fn init_postload_fpga(&mut self) {
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// Enable level shifters
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self.lvl_shftr_en.write(
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LvlShftr::zeroed()
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.user_lvl_shftr_en(LevelShifterEnable::EnableAll)
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);
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// Deassert AXI interface resets
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self.fpga_rst_ctrl.write(
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FpgaRstCtrl::zeroed()
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);
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}
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}
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register!(slcr_lock, SlcrLock, WO, u32);
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@ -453,6 +492,12 @@ register!(lqspi_rst_ctrl, LqspiRstCtrl, RW, u32);
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register_bit!(lqspi_rst_ctrl, ref_rst, 1);
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register_bit!(lqspi_rst_ctrl, cpu1x_rst, 0);
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register!(fpga_rst_ctrl, FpgaRstCtrl, RW, u32);
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register_bit!(fpga_rst_ctrl, fpga0_out_rst, 0);
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register_bit!(fpga_rst_ctrl, fpga1_out_rst, 1);
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register_bit!(fpga_rst_ctrl, fpga2_out_rst, 2);
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register_bit!(fpga_rst_ctrl, fpga3_out_rst, 3);
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register!(a9_cpu_rst_ctrl, A9CpuRstCtrl, RW, u32);
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register_bit!(a9_cpu_rst_ctrl, peri_rst, 8);
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register_bit!(a9_cpu_rst_ctrl, a9_clkstop1, 5);
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@ -556,6 +601,9 @@ mio_pin_register!(mio_pin_51, MioPin51);
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mio_pin_register!(mio_pin_52, MioPin52);
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mio_pin_register!(mio_pin_53, MioPin53);
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register!(lvl_shftr, LvlShftr, RW, u32);
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register_bits_typed!(lvl_shftr, user_lvl_shftr_en, u8, LevelShifterEnable, 0, 3);
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register!(gpiob_ctrl, GpiobCtrl, RW, u32);
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register_bit!(gpiob_ctrl, vref_en, 0);
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