forked from M-Labs/zynq-rs
zynq::ddr: fix DDR 3x/2x setup, print clocks
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ff96bf903b
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261455877d
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@ -42,8 +42,9 @@ impl DdrRam {
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let clocks = CpuClocks::get();
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println!("Clocks: {:?}", clocks);
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let ddr3x_clk_divisor = ((clocks.ddr - 1) / DDR_FREQ + 1).min(255) as u8;
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let ddr3x_clk_divisor = ((DDR_FREQ - 1 + clocks.ddr) / DDR_FREQ).min(255) as u8;
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let ddr2x_clk_divisor = 3 * ddr3x_clk_divisor / 2;
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println!("DDR 3x/2x clocks: {}/{}", clocks.ddr / u32::from(ddr3x_clk_divisor), clocks.ddr / u32::from(ddr2x_clk_divisor));
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.ddr_clk_ctrl.write(
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@ -64,6 +65,7 @@ impl DdrRam {
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.max(1).min(63) as u8;
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let divisor1 = (clocks.ddr / DCI_FREQ / u32::from(divisor0))
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.max(1).min(63) as u8;
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println!("DDR DCI clock: {} Hz", clocks.ddr / u32::from(divisor0) / u32::from(divisor1));
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slcr::RegisterBlock::unlocked(|slcr| {
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// Step 1.
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