forked from M-Labs/zynq-rs
cortex_a9: add proper L1 cache invalidation
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@ -0,0 +1,206 @@
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/// Invalidate TLBs
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#[inline(always)]
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pub fn tlbiall() {
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unsafe {
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asm!("mcr p15, 0, $0, c8, c7, 0" :: "r" (0) :: "volatile");
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}
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}
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/// Invalidate I-Cache
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#[inline(always)]
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pub fn iciallu() {
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unsafe {
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asm!("mcr p15, 0, $0, c7, c5, 0" :: "r" (0) :: "volatile");
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}
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}
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/// Invalidate Branch Predictor Array
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#[inline(always)]
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pub fn bpiall() {
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unsafe {
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asm!("mcr p15, 0, $0, c7, c5, 6" :: "r" (0) :: "volatile");
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}
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}
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#[inline(always)]
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pub fn dcisw(setway: u32) {
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unsafe {
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// acc. to ARM Architecture Reference Manual, Figure B3-32;
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// also see example code (for DCCISW, but DCISW will be
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// analogous) "Example code for cache maintenance operations"
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// on pages B2-1286 and B2-1287.
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asm!("mcr p15, 0, $0, c7, c6, 2" :: "r" (setway) :: "volatile");
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}
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}
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/// A made-up "instruction": invalidate all of the L1 D-Cache
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#[inline(always)]
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pub fn dciall() {
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// the cache associativity could be read from a register, but will
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// always be 4 in L1 data cache of a cortex a9
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let ways = 4;
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let bit_pos_of_way = 30; // 32 - log2(ways)
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// the cache sets could be read from a register, but are always
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// 256 for the cores in the zync-7000; in general, 128 or 512 are
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// also possible.
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let sets = 256;
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let bit_pos_of_set = 5; // for a line size of 8 words = 2^5 bytes
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// select L1 data cache
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unsafe {
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asm!("mcr p15, 2, $0, c0, c0, 0" :: "r" (0) :: "volatile");
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}
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// Invalidate entire D-Cache by iterating every set and every way
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for set in 0..sets {
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for way in 0..ways {
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dcisw((set << bit_pos_of_set) | (way << bit_pos_of_way));
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}
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}
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}
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/// Data cache clear and invalidate by memory virtual address. This
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/// flushes data out to the point of coherency, and invalidates the
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/// corresponding cache line (as appropriate when DMA is meant to be
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/// writing into it).
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#[inline(always)]
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pub fn dccimva(addr: usize) {
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unsafe {
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asm!("mcr p15, 0, $0, c7, c14, 1" :: "r" (addr) :: "volatile");
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}
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}
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/// The DCCIVMA (data cache clear and invalidate) applied to the
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/// region of memory occupied by the argument. This does not modify
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/// the argument, but due to the invalidate part (only ever needed if
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/// external write access is to be granted, e.g. by DMA) it only makes
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/// sense if the caller has exclusive access to it as otherwise other
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/// accesses might just bring it back into the data cache.
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pub fn dcci<T>(object: &mut T) {
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let cache_line = 0x20;
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let first_addr =
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(object as *mut _ as *const _ as usize) & !(cache_line - 1);
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let beyond_addr = (
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(object as *mut _ as *const _ as usize)
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+ core::mem::size_of_val(object)
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+ (cache_line - 1)
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) & !(cache_line - 1);
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for addr in (first_addr..beyond_addr).step_by(cache_line) {
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dccimva(addr);
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}
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}
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pub fn dcci_slice_content<T>(slice: &mut [T]) {
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if slice.len() == 0 {
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return;
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}
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let cache_line = 0x20;
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let first_addr =
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(&slice[0] as *const _ as usize) & !(cache_line - 1);
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let beyond_addr = (
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(&slice[slice.len() - 1] as *const _ as usize)
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+ (cache_line - 1)
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) & !(cache_line - 1);
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for addr in (first_addr..beyond_addr).step_by(cache_line) {
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dccimva(addr);
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}
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}
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pub fn dcci_slice_content_unmut<T>(slice: &[T]) {
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if slice.len() == 0 {
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return;
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}
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let cache_line = 0x20;
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let first_addr =
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(&slice[0] as *const _ as usize) & !(cache_line - 1);
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let beyond_addr = (
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(&slice[slice.len() - 1] as *const _ as usize)
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+ (cache_line - 1)
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) & !(cache_line - 1);
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for addr in (first_addr..beyond_addr).step_by(cache_line) {
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dccimva(addr);
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}
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}
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/// Data cache invalidate by memory virtual address. This and
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/// invalidates the cache line containing the given address. Super
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/// unsafe, as this discards a write-back cache line, potentially
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/// affecting more data than intended.
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#[inline(always)]
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pub unsafe fn dcimva(addr: usize) {
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asm!("mcr p15, 0, $0, c7, c6, 1" :: "r" (addr) :: "volatile");
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}
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/// Data cache invalidate for an object. Panics if not properly
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/// aligned and properly sized to be contained in an exact number of
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/// cache lines.
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pub fn dci<T>(object: &mut T) {
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let cache_line = 0x20;
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let first_addr = object as *mut _ as *const _ as usize;
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let beyond_addr = (object as *mut _ as *const _ as usize) +
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core::mem::size_of_val(object);
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assert_eq!((first_addr & (cache_line - 1)), 0x00);
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assert_eq!((beyond_addr & (cache_line - 1)), 0x00);
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for addr in (first_addr..beyond_addr).step_by(cache_line) {
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unsafe {
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dcimva(addr);
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}
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}
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}
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/// Data cache invalidate for the contents of a slice. Panics if not
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/// properly aligned and properly sized to be contained in an exact
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/// number of cache lines.
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pub fn dci_slice_content<T>(slice: &mut [T]) {
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if slice.len() == 0 {
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return;
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}
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let cache_line = 0x20;
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let first_addr = &slice[0] as *const _ as usize;
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let beyond_addr = (&slice[slice.len() - 1] as *const _ as usize)
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+ core::mem::size_of::<T>();
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assert_eq!((first_addr & (cache_line - 1)), 0x00);
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assert_eq!((beyond_addr & (cache_line - 1)), 0x00);
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for addr in (first_addr..beyond_addr).step_by(cache_line) {
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unsafe {
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dcimva(addr);
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}
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}
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}
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pub unsafe fn dci_more_than_slice_content<T>(slice: &mut [T]) {
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if slice.len() == 0 {
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return;
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}
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let cache_line = 0x20;
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let first_addr =
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(&slice[0] as *const _ as usize) & !(cache_line - 1);
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let beyond_addr = (
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(&slice[slice.len() - 1] as *const _ as usize)
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+ (cache_line - 1)
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) & !(cache_line - 1);
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assert_eq!((first_addr & (cache_line - 1)), 0x00);
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assert_eq!((beyond_addr & (cache_line - 1)), 0x00);
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for addr in (first_addr..beyond_addr).step_by(cache_line) {
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dcimva(addr);
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}
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}
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pub unsafe fn dci_more_than_slice_content_nonmut<T>(slice: &[T]) {
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if slice.len() == 0 {
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return;
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}
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let cache_line = 0x20;
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let first_addr =
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(&slice[0] as *const _ as usize) & !(cache_line - 1);
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let beyond_addr = (
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(&slice[slice.len() - 1] as *const _ as usize)
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+ (cache_line - 1)
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) & !(cache_line - 1);
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assert_eq!((first_addr & (cache_line - 1)), 0x00);
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assert_eq!((beyond_addr & (cache_line - 1)), 0x00);
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for addr in (first_addr..beyond_addr).step_by(cache_line) {
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dcimva(addr);
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}
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}
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@ -1,5 +1,6 @@
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pub mod asm;
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pub mod regs;
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pub mod cache;
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pub mod mmu;
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global_asm!(include_str!("exceptions.s"));
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@ -136,36 +136,3 @@ register_bit!(ttbr,
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/// Translation table walk to shared memory?
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s, 1);
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register_bit!(ttbr, irgn1, 0);
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/// Invalidate TLBs
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#[inline(always)]
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pub fn tlbiall() {
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unsafe {
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asm!("mcr p15, 0, $0, c8, c7, 0" :: "r" (0) :: "volatile");
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}
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}
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/// Invalidate I-Cache
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#[inline(always)]
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pub fn iciallu() {
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unsafe {
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asm!("mcr p15, 0, $0, c7, c5, 0" :: "r" (0) :: "volatile");
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}
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}
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/// Invalidate Branch Predictor Array
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#[inline(always)]
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pub fn bpiall() {
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unsafe {
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asm!("mcr p15, 0, $0, c7, c5, 6" :: "r" (0) :: "volatile");
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}
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}
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/// Invalidate D-Cache
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#[inline(always)]
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pub fn dccisw() {
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// TODO: $0 is r11 at what value?
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unsafe {
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asm!("mcr p15, 0, $0, c7, c5, 6" :: "r" (0) :: "volatile");
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}
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}
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11
src/main.rs
11
src/main.rs
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@ -66,6 +66,8 @@ unsafe fn boot_core0() -> ! {
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}
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fn l1_cache_init() {
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use crate::cortex_a9::cache::*;
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// Invalidate TLBs
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tlbiall();
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// Invalidate I-Cache
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@ -73,7 +75,14 @@ fn l1_cache_init() {
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// Invalidate Branch Predictor Array
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bpiall();
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// Invalidate D-Cache
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dccisw();
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//
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// NOTE: It is both faster and correct to only invalidate instead
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// of also flush the cache (as was done before with
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// `dccisw()`) and it is correct to perform this operation
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// for all of the L1 data cache rather than a (previously
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// unspecified) combination of one cache set and one cache
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// way.
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dciall();
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}
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const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
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