2019-03-07 23:27:33 +08:00
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#![no_std]
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#![no_main]
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2020-03-12 06:17:17 +08:00
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// TODO: #![deny(warnings, unused)]
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2019-03-07 23:27:33 +08:00
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2019-03-15 02:58:41 +08:00
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#[cfg(not(feature = "semihosting"))]
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2019-04-27 21:23:50 +08:00
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use panic_abort as _;
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2019-03-15 02:58:41 +08:00
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#[cfg(feature = "semihosting")]
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2019-04-27 21:23:50 +08:00
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use panic_semihosting as _;
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2019-03-07 23:27:33 +08:00
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2019-04-27 21:23:50 +08:00
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use log::{info, warn};
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2019-03-15 02:58:41 +08:00
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2020-03-20 01:34:57 +08:00
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use core::ops::DerefMut;
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2019-03-15 02:58:41 +08:00
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use core::fmt::Write;
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2019-03-12 01:23:52 +08:00
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use cortex_m::asm::wfi;
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2019-03-07 23:27:33 +08:00
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use cortex_m_rt::entry;
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2019-03-12 01:23:52 +08:00
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use stm32f4xx_hal::{
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2020-03-20 01:34:57 +08:00
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hal::{
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self,
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2020-03-21 07:33:31 +08:00
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digital::v2::OutputPin,
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2020-03-20 01:34:57 +08:00
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watchdog::{WatchdogEnable, Watchdog},
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},
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2019-03-12 01:23:52 +08:00
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rcc::RccExt,
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watchdog::IndependentWatchdog,
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2020-03-13 01:31:43 +08:00
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time::{U32Ext, MegaHertz},
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2019-03-12 01:23:52 +08:00
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stm32::{CorePeripherals, Peripherals},
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};
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2019-03-22 00:41:33 +08:00
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use smoltcp::{
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time::Instant,
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wire::EthernetAddress,
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};
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2019-03-12 01:23:52 +08:00
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2020-03-12 07:50:24 +08:00
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mod init_log;
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use init_log::init_log;
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2020-03-09 07:27:35 +08:00
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mod pins;
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2020-03-12 06:16:48 +08:00
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use pins::Pins;
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mod ad7172;
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2020-03-13 04:27:03 +08:00
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mod ad5680;
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2019-03-13 05:52:39 +08:00
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mod net;
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mod server;
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use server::Server;
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2020-03-14 06:39:22 +08:00
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mod session;
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use session::{CHANNELS, Session, SessionOutput};
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mod command_parser;
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2020-03-20 01:34:57 +08:00
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use command_parser::{Command, ShowCommand, PwmPin};
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2019-03-15 01:13:25 +08:00
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mod timer;
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2020-03-19 04:51:30 +08:00
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mod pid;
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mod steinhart_hart;
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2020-03-20 05:09:16 +08:00
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mod channel_state;
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use channel_state::ChannelState;
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2020-03-14 06:39:22 +08:00
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2019-03-07 23:27:33 +08:00
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2020-03-20 01:34:57 +08:00
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const HSE: MegaHertz = MegaHertz(8);
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2020-03-12 06:17:34 +08:00
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#[cfg(not(feature = "semihosting"))]
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const WATCHDOG_INTERVAL: u32 = 100;
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#[cfg(feature = "semihosting")]
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const WATCHDOG_INTERVAL: u32 = 10_000;
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2019-03-22 00:41:33 +08:00
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#[cfg(not(feature = "generate-hwaddr"))]
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const NET_HWADDR: [u8; 6] = [0x02, 0x00, 0xDE, 0xAD, 0xBE, 0xEF];
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2020-03-14 06:39:22 +08:00
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const TCP_PORT: u16 = 23;
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2019-03-15 02:58:41 +08:00
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2020-03-13 01:31:43 +08:00
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2019-03-19 04:41:51 +08:00
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/// Initialization and main loop
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2019-03-07 23:27:33 +08:00
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#[entry]
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fn main() -> ! {
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2019-03-15 02:58:41 +08:00
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init_log();
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2020-03-14 06:39:22 +08:00
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info!("tecpak");
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2019-03-12 01:23:52 +08:00
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let mut cp = CorePeripherals::take().unwrap();
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2019-03-13 05:52:39 +08:00
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cp.SCB.enable_icache();
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cp.SCB.enable_dcache(&mut cp.CPUID);
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2019-03-12 01:23:52 +08:00
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let dp = Peripherals::take().unwrap();
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stm32_eth::setup(&dp.RCC, &dp.SYSCFG);
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2020-03-13 01:31:43 +08:00
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2019-03-15 01:13:25 +08:00
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let clocks = dp.RCC.constrain()
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2019-03-12 01:23:52 +08:00
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.cfgr
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2020-03-13 01:31:43 +08:00
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.use_hse(HSE)
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2019-03-19 05:04:34 +08:00
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.sysclk(168.mhz())
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.hclk(168.mhz())
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.pclk1(32.mhz())
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.pclk2(64.mhz())
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2019-03-12 01:23:52 +08:00
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.freeze();
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let mut wd = IndependentWatchdog::new(dp.IWDG);
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2020-03-12 06:17:34 +08:00
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wd.start(WATCHDOG_INTERVAL.ms());
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2019-03-12 01:23:52 +08:00
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wd.feed();
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2020-03-13 00:26:14 +08:00
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let pins = Pins::setup(
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clocks, dp.TIM1, dp.TIM3,
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2020-03-13 02:24:57 +08:00
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dp.GPIOA, dp.GPIOB, dp.GPIOC, dp.GPIOE, dp.GPIOF, dp.GPIOG,
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dp.SPI2, dp.SPI4, dp.SPI5
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2020-03-13 00:26:14 +08:00
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);
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2019-03-12 01:23:52 +08:00
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2020-03-12 06:16:48 +08:00
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let mut adc = ad7172::Adc::new(pins.adc_spi, pins.adc_nss).unwrap();
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2020-03-21 07:36:52 +08:00
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// Feature not used
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adc.set_sync_enable(false).unwrap();
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// Setup channels
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2020-03-20 07:45:10 +08:00
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adc.setup_channel(0, ad7172::Input::Ain0, ad7172::Input::Ain1).unwrap();
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adc.setup_channel(1, ad7172::Input::Ain2, ad7172::Input::Ain3).unwrap();
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2020-03-21 06:51:19 +08:00
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adc.calibrate_offset().unwrap();
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2020-03-21 07:46:24 +08:00
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2020-03-13 04:27:03 +08:00
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let mut dac0 = ad5680::Dac::new(pins.dac0_spi, pins.dac0_sync);
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2020-03-20 01:34:57 +08:00
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dac0.set(0).unwrap();
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2020-03-13 04:27:03 +08:00
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let mut dac1 = ad5680::Dac::new(pins.dac1_spi, pins.dac1_sync);
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2020-03-20 01:34:57 +08:00
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dac1.set(0).unwrap();
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2020-03-21 07:46:24 +08:00
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2020-03-20 01:34:57 +08:00
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let mut pwm = pins.pwm;
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2020-03-21 07:33:31 +08:00
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let mut shdn0 = pins.shdn0;
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let mut shdn1 = pins.shdn1;
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2019-03-15 01:13:25 +08:00
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timer::setup(cp.SYST, clocks);
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2019-03-22 00:41:33 +08:00
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#[cfg(not(feature = "generate-hwaddr"))]
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let hwaddr = EthernetAddress(NET_HWADDR);
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#[cfg(feature = "generate-hwaddr")]
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let hwaddr = {
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let uid = stm32f4xx_hal::signature::Uid::get();
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EthernetAddress(hash2hwaddr::generate_hwaddr(uid))
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};
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info!("Net hwaddr: {}", hwaddr);
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2020-03-20 01:34:57 +08:00
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let mut channel_states: [ChannelState; CHANNELS] = [
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ChannelState::default(), ChannelState::default()
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];
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2020-03-14 06:39:22 +08:00
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2020-03-09 07:07:56 +08:00
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net::run(dp.ETHERNET_MAC, dp.ETHERNET_DMA, hwaddr, |iface| {
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2020-03-14 06:39:22 +08:00
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Server::<Session>::run(iface, |server| {
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2019-03-19 03:02:57 +08:00
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loop {
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2020-03-21 07:07:18 +08:00
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let instant = Instant::from_millis(i64::from(timer::now()));
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2020-03-14 06:39:22 +08:00
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// ADC input
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adc.data_ready().unwrap().map(|channel| {
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2020-03-12 07:44:15 +08:00
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let data = adc.read_data().unwrap();
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2020-03-14 06:39:22 +08:00
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let state = &mut channel_states[usize::from(channel)];
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2020-03-20 05:09:16 +08:00
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state.update_adc(instant, data);
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if state.pid_enabled {
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// Forward PID output to i_set DAC
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match channel {
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2020-03-21 07:33:31 +08:00
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0 => {
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dac0.set(state.dac_value).unwrap();
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shdn0.set_high().unwrap();
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}
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1 => {
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dac1.set(state.dac_value).unwrap();
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shdn1.set_high().unwrap();
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}
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2020-03-20 05:09:16 +08:00
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_ =>
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unreachable!(),
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}
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}
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2020-03-14 06:39:22 +08:00
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server.for_each(|_, session| session.set_report_pending(channel.into()));
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});
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2020-03-21 07:46:24 +08:00
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let instant = Instant::from_millis(i64::from(timer::now()));
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cortex_m::interrupt::free(net::clear_pending);
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server.poll(instant)
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.unwrap_or_else(|e| {
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warn!("poll: {:?}", e);
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});
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2020-03-14 06:39:22 +08:00
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// TCP protocol handling
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server.for_each(|mut socket, session| {
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2020-03-21 07:37:24 +08:00
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if ! socket.is_active() {
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2020-03-14 06:39:22 +08:00
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let _ = socket.listen(TCP_PORT);
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2020-03-21 06:20:38 +08:00
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session.reset();
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2020-03-21 07:11:23 +08:00
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} else if socket.can_send() && socket.can_recv() && socket.send_capacity() - socket.send_queue() > 1024 {
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2020-03-14 06:39:22 +08:00
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match socket.recv(|buf| session.feed(buf)) {
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Ok(SessionOutput::Nothing) => {}
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Ok(SessionOutput::Command(command)) => match command {
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Command::Quit =>
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socket.close(),
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Command::Reporting(reporting) => {
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let _ = writeln!(socket, "report={}", if reporting { "on" } else { "off" });
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}
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Command::Show(ShowCommand::Reporting) => {
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let _ = writeln!(socket, "report={}", if session.reporting() { "on" } else { "off" });
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}
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Command::Show(ShowCommand::Input) => {
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for (channel, state) in channel_states.iter().enumerate() {
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if let Some(adc_data) = state.adc_data {
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let _ = writeln!(
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socket, "t={} raw{}=0x{:06X}",
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state.adc_time, channel, adc_data
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);
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}
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}
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}
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Command::Show(ShowCommand::Pid) => {
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2020-03-20 01:34:57 +08:00
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for (channel, state) in channel_states.iter().enumerate() {
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let _ = writeln!(socket, "PID settings for channel {}", channel);
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let pid = &state.pid;
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2020-03-20 05:00:22 +08:00
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let _ = writeln!(socket, "- target={:.4}", pid.target);
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macro_rules! show_pid_parameter {
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2020-03-20 01:34:57 +08:00
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($p: tt) => {
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2020-03-20 05:00:22 +08:00
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let _ = writeln!(
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socket, "- {}={:.4}",
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stringify!($p), pid.parameters.$p
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);
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2020-03-20 01:34:57 +08:00
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};
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}
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2020-03-20 05:00:22 +08:00
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show_pid_parameter!(kp);
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show_pid_parameter!(ki);
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show_pid_parameter!(kd);
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show_pid_parameter!(output_min);
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show_pid_parameter!(output_max);
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show_pid_parameter!(integral_min);
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show_pid_parameter!(integral_max);
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if let Some(last_output) = pid.last_output {
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let _ = writeln!(socket, "- output={:.4}", last_output);
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}
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2020-03-20 01:34:57 +08:00
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let _ = writeln!(socket, "");
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}
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2020-03-14 06:39:22 +08:00
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}
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Command::Show(ShowCommand::Pwm) => {
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2020-03-20 01:34:57 +08:00
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for (channel, state) in channel_states.iter().enumerate() {
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let _ = writeln!(
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socket, "channel {}: PID={}",
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channel,
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if state.pid_enabled { "engaged" } else { "disengaged" }
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);
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let _ = writeln!(socket, "- i_set={}/{}", state.dac_value, ad5680::MAX_VALUE);
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fn show_pwm_channel<S, P>(mut socket: S, name: &str, pin: &P)
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where
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S: core::fmt::Write,
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P: hal::PwmPin<Duty=u16>,
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{
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let _ = writeln!(
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socket,
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"- {}={}/{}",
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name, pin.get_duty(), pin.get_max_duty()
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);
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}
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match channel {
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0 => {
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show_pwm_channel(socket.deref_mut(), "max_v", &pwm.max_v0);
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show_pwm_channel(socket.deref_mut(), "max_i_pos", &pwm.max_i_pos0);
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show_pwm_channel(socket.deref_mut(), "max_i_neg", &pwm.max_i_neg0);
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}
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1 => {
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show_pwm_channel(socket.deref_mut(), "max_v", &pwm.max_v1);
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show_pwm_channel(socket.deref_mut(), "max_i_pos", &pwm.max_i_pos1);
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show_pwm_channel(socket.deref_mut(), "max_i_neg", &pwm.max_i_neg1);
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}
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_ => unreachable!(),
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}
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let _ = writeln!(socket, "");
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}
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2020-03-14 06:39:22 +08:00
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}
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Command::Show(ShowCommand::SteinhartHart) => {
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2020-03-20 01:34:57 +08:00
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for (channel, state) in channel_states.iter().enumerate() {
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let _ = writeln!(
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socket, "channel {}: Steinhart-Hart equation parameters",
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channel,
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);
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let _ = writeln!(socket, "- t0={}", state.sh.t0);
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2020-03-20 05:56:14 +08:00
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let _ = writeln!(socket, "- b={}", state.sh.b);
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2020-03-20 01:34:57 +08:00
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let _ = writeln!(socket, "- r0={}", state.sh.r0);
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let _ = writeln!(socket, "");
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}
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2020-03-14 06:39:22 +08:00
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}
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Command::Show(ShowCommand::PostFilter) => {
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2020-03-20 01:34:57 +08:00
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for (channel, _) in channel_states.iter().enumerate() {
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match adc.get_postfilter(channel as u8).unwrap() {
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Some(filter) => {
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let _ = writeln!(
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socket, "channel {}: postfilter={:.2} SPS",
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channel, filter.output_rate().unwrap()
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);
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}
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None => {
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let _ = writeln!(
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socket, "channel {}: no postfilter",
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channel
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);
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}
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}
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}
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}
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Command::PwmPid { channel } => {
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|
channel_states[channel].pid_enabled = true;
|
|
|
|
let _ = writeln!(socket, "channel {}: PID enabled to control PWM", channel
|
|
|
|
);
|
|
|
|
}
|
|
|
|
Command::Pwm { channel, pin: PwmPin::ISet, duty } if duty <= ad5680::MAX_VALUE => {
|
|
|
|
channel_states[channel].pid_enabled = false;
|
|
|
|
match channel {
|
2020-03-21 07:33:31 +08:00
|
|
|
0 => {
|
|
|
|
dac0.set(duty).unwrap();
|
|
|
|
shdn0.set_high().unwrap();
|
|
|
|
}
|
|
|
|
1 => {
|
|
|
|
dac1.set(duty).unwrap();
|
|
|
|
shdn1.set_high().unwrap();
|
|
|
|
}
|
2020-03-20 01:34:57 +08:00
|
|
|
_ => unreachable!(),
|
|
|
|
}
|
|
|
|
channel_states[channel].dac_value = duty;
|
|
|
|
let _ = writeln!(
|
|
|
|
socket, "channel {}: PWM duty cycle manually set to {}/{}",
|
|
|
|
channel, duty, ad5680::MAX_VALUE
|
|
|
|
);
|
2020-03-14 06:39:22 +08:00
|
|
|
}
|
2020-03-20 01:34:57 +08:00
|
|
|
Command::Pwm { pin: PwmPin::ISet, duty, .. } if duty > ad5680::MAX_VALUE => {
|
|
|
|
let _ = writeln!(
|
|
|
|
socket, "error: PWM duty range must not exceed {}",
|
|
|
|
ad5680::MAX_VALUE
|
|
|
|
);
|
2020-03-14 06:39:22 +08:00
|
|
|
}
|
2020-03-20 01:34:57 +08:00
|
|
|
Command::Pwm { channel, pin, duty } if duty <= 0xFFFF => {
|
|
|
|
let duty = duty as u16;
|
|
|
|
|
|
|
|
fn set_pwm_channel<P: hal::PwmPin<Duty=u16>>(pin: &mut P, duty: u16) -> u16 {
|
|
|
|
pin.set_duty(duty);
|
|
|
|
pin.get_max_duty()
|
|
|
|
}
|
|
|
|
let max = match (channel, pin) {
|
|
|
|
(_, PwmPin::ISet) =>
|
|
|
|
// Handled above
|
|
|
|
unreachable!(),
|
|
|
|
(0, PwmPin::MaxIPos) =>
|
|
|
|
set_pwm_channel(&mut pwm.max_i_pos0, duty),
|
|
|
|
(0, PwmPin::MaxINeg) =>
|
|
|
|
set_pwm_channel(&mut pwm.max_i_neg0, duty),
|
|
|
|
(0, PwmPin::MaxV) =>
|
|
|
|
set_pwm_channel(&mut pwm.max_v0, duty),
|
|
|
|
(1, PwmPin::MaxIPos) =>
|
|
|
|
set_pwm_channel(&mut pwm.max_i_pos1, duty),
|
|
|
|
(1, PwmPin::MaxINeg) =>
|
|
|
|
set_pwm_channel(&mut pwm.max_i_neg1, duty),
|
|
|
|
(1, PwmPin::MaxV) =>
|
|
|
|
set_pwm_channel(&mut pwm.max_v1, duty),
|
|
|
|
_ =>
|
|
|
|
unreachable!(),
|
|
|
|
};
|
|
|
|
let _ = writeln!(
|
|
|
|
socket, "channel {}: PWM {} reconfigured to {}/{}",
|
|
|
|
channel, pin.name(), duty, max
|
|
|
|
);
|
2020-03-14 06:39:22 +08:00
|
|
|
}
|
2020-03-20 01:34:57 +08:00
|
|
|
Command::Pwm { duty, .. } if duty > 0xFFFF => {
|
|
|
|
let _ = writeln!(socket, "error: PWM duty range must fit 16 bits");
|
2020-03-14 06:39:22 +08:00
|
|
|
}
|
|
|
|
Command::Pid { channel, parameter, value } => {
|
2020-03-20 01:34:57 +08:00
|
|
|
let pid = &mut channel_states[channel].pid;
|
|
|
|
use command_parser::PidParameter::*;
|
|
|
|
match parameter {
|
|
|
|
Target =>
|
2020-03-20 05:01:16 +08:00
|
|
|
pid.target = value,
|
2020-03-20 01:34:57 +08:00
|
|
|
KP =>
|
2020-03-20 05:01:16 +08:00
|
|
|
pid.parameters.kp = value,
|
2020-03-20 01:34:57 +08:00
|
|
|
KI =>
|
2020-03-20 05:01:16 +08:00
|
|
|
pid.parameters.ki = value,
|
2020-03-20 01:34:57 +08:00
|
|
|
KD =>
|
2020-03-20 05:01:16 +08:00
|
|
|
pid.parameters.kd = value,
|
2020-03-20 01:34:57 +08:00
|
|
|
OutputMin =>
|
2020-03-20 05:01:16 +08:00
|
|
|
pid.parameters.output_min = value,
|
2020-03-20 01:34:57 +08:00
|
|
|
OutputMax =>
|
2020-03-20 05:01:16 +08:00
|
|
|
pid.parameters.output_max = value,
|
2020-03-20 01:34:57 +08:00
|
|
|
IntegralMin =>
|
2020-03-20 05:01:16 +08:00
|
|
|
pid.parameters.integral_min = value,
|
2020-03-20 01:34:57 +08:00
|
|
|
IntegralMax =>
|
2020-03-20 05:01:16 +08:00
|
|
|
pid.parameters.integral_max = value,
|
2020-03-20 01:34:57 +08:00
|
|
|
}
|
2020-03-20 05:01:16 +08:00
|
|
|
// TODO: really reset PID state
|
|
|
|
// after each parameter change?
|
2020-03-20 01:34:57 +08:00
|
|
|
pid.reset();
|
|
|
|
let _ = writeln!(socket, "PID parameter updated");
|
2020-03-14 06:39:22 +08:00
|
|
|
}
|
|
|
|
Command::SteinhartHart { channel, parameter, value } => {
|
2020-03-20 01:34:57 +08:00
|
|
|
let sh = &mut channel_states[channel].sh;
|
|
|
|
use command_parser::ShParameter::*;
|
|
|
|
match parameter {
|
|
|
|
T0 => sh.t0 = value,
|
2020-03-20 05:56:14 +08:00
|
|
|
B => sh.b = value,
|
2020-03-20 01:34:57 +08:00
|
|
|
R0 => sh.r0 = value,
|
|
|
|
}
|
|
|
|
let _ = writeln!(socket, "Steinhart-Hart equation parameter updated");
|
2020-03-14 06:39:22 +08:00
|
|
|
}
|
|
|
|
Command::PostFilter { channel, rate } => {
|
2020-03-20 01:34:57 +08:00
|
|
|
let filter = ad7172::PostFilter::closest(rate);
|
|
|
|
match filter {
|
|
|
|
Some(filter) => {
|
|
|
|
adc.set_postfilter(channel as u8, Some(filter)).unwrap();
|
|
|
|
let _ = writeln!(
|
|
|
|
socket, "channel {}: postfilter set to {:.2} SPS",
|
|
|
|
channel, filter.output_rate().unwrap()
|
|
|
|
);
|
|
|
|
}
|
|
|
|
None => {
|
|
|
|
let _ = writeln!(socket, "Unable to choose postfilter");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
cmd => {
|
|
|
|
let _ = writeln!(socket, "Not yet implemented: {:?}", cmd);
|
2020-03-14 06:39:22 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
Ok(SessionOutput::Error(e)) => {
|
|
|
|
let _ = writeln!(socket, "Command error: {:?}", e);
|
|
|
|
}
|
|
|
|
Err(_) =>
|
|
|
|
socket.close(),
|
|
|
|
}
|
|
|
|
} else if socket.can_send() && socket.send_capacity() - socket.send_queue() > 256 {
|
|
|
|
while let Some(channel) = session.is_report_pending() {
|
|
|
|
let state = &mut channel_states[usize::from(channel)];
|
|
|
|
let _ = writeln!(
|
2020-03-21 07:11:03 +08:00
|
|
|
socket, "t={} raw{}=0x{:06X}",
|
2020-03-14 06:39:22 +08:00
|
|
|
state.adc_time, channel, state.adc_data.unwrap_or(0)
|
|
|
|
).map(|_| {
|
|
|
|
session.mark_report_sent(channel);
|
|
|
|
});
|
|
|
|
}
|
|
|
|
}
|
|
|
|
});
|
2020-03-12 07:44:15 +08:00
|
|
|
|
2019-03-19 03:02:57 +08:00
|
|
|
// Update watchdog
|
|
|
|
wd.feed();
|
|
|
|
|
2020-03-21 07:46:24 +08:00
|
|
|
cortex_m::interrupt::free(|cs| {
|
|
|
|
if !net::is_pending(cs) {
|
|
|
|
// Wait for interrupts
|
|
|
|
// (Ethernet or SysTick)
|
|
|
|
wfi();
|
|
|
|
}
|
|
|
|
});
|
2019-03-15 01:13:25 +08:00
|
|
|
}
|
2019-03-19 03:02:57 +08:00
|
|
|
});
|
|
|
|
});
|
2019-03-15 03:43:35 +08:00
|
|
|
|
2019-03-19 04:17:27 +08:00
|
|
|
unreachable!()
|
2019-03-07 23:27:33 +08:00
|
|
|
}
|