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406 Commits

Author SHA1 Message Date
mwojcik c536a70890 satellite gateware: add rtio analyzer 2023-05-22 15:23:24 +08:00
mwojcik 259b0ba1b7 satellite: port analyzer, drtio packets 2023-05-22 15:23:23 +08:00
mwojcik cbc660e740 ddma: pass "uses_ddma" flag 2023-04-18 12:36:07 +08:00
Jonathan Coates 8cb6cf6094 Fix mismatched signatures for the wide interface 
Lists are passed by-reference from python code, and so should be
&CSlice<_> not CSlice<_>.
 2023-04-17 09:24:30 +08:00
Egor Savkin c6fcc4e351 Add ext0_synth0_80to125 option to the clocker config 
Signed-off-by: Egor Savkin <es@m-labs.hk>
 2023-04-13 12:08:25 +08:00
Sebastien Bourdeauducq bf50a44f76 cargo fmt 2023-04-04 11:48:48 +08:00
Sebastien Bourdeauducq 64cadd90f5 fix imports 2023-04-04 11:23:11 +08:00
Sebastien Bourdeauducq 271a1adb04 firmware: improve RTIO map error reporting 2023-04-04 11:17:26 +08:00
mwojcik b747abe83c qc2: add 4 edge counters to the end of rtio 2023-04-03 12:25:07 +08:00
mwojcik 48721ca9cb apply rustfmt policies to ddma code 2023-03-27 15:53:32 +08:00
mwojcik 90071f7620 Master: DDMA support 
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
 2023-03-27 15:47:54 +08:00
mwojcik 908dfc780e satman: add dma support 2023-03-23 11:04:26 +08:00
mwojcik 4b1ce1a6ff satellites: add rtio_dma, connect as cri master 2023-03-21 15:54:58 +08:00
Egor Savkin a519d24074 firmware: create and apply rustfmt policy 
Co-authored-by: Egor Savkin <es@m-labs.hk>
Co-committed-by: Egor Savkin <es@m-labs.hk>
 2023-02-22 11:02:43 +08:00
mwojcik dce37a52aa KasliSoC satellite: fix serdes timing 2023-02-20 13:07:42 +08:00
Egor Savkin d72a2e7d07 fix previous commit 
Co-authored-by: Egor Savkin <es@m-labs.hk>
Co-committed-by: Egor Savkin <es@m-labs.hk>
 2023-02-17 17:49:36 +08:00
Egor Savkin 05c22792d6 satman: drive SFP TX_DISABLE 
Co-authored-by: Egor Savkin <es@m-labs.hk>
Co-committed-by: Egor Savkin <es@m-labs.hk>
 2023-02-17 17:19:30 +08:00
mwojcik dcc5cc7555 satellite: add Error LED on panic 2023-02-17 16:21:52 +08:00
mwojcik 46b2687d70 RTIO/SYS Clock merge 
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
 2023-02-17 15:52:43 +08:00
Egor Savkin ca6e0d13ad Remove virtual LEDs from io_expander 
Signed-off-by: Egor Savkin <es@m-labs.hk>
 2023-02-15 18:14:05 +08:00
Egor Savkin b4b7912c40 Port tx_disable-related code from Kasli 
Signed-off-by: Egor Savkin <es@m-labs.hk>
 2023-02-15 17:44:01 +08:00
Egor Savkin 8230a01701 Build io_expander 
Signed-off-by: Egor Savkin <es@m-labs.hk>
 2023-02-15 15:31:22 +08:00
Egor Savkin 4bc936f071 Copy io expander from kasli 
Signed-off-by: Egor Savkin <es@m-labs.hk>
 2023-02-15 14:37:55 +08:00
David Nadlinger df4988c774 rpc: Port over size/alignment fix for structs (tuples) with tail padding 
This ports over the following commits from the main ARTIQ repo:
 - 8740ec3dd52d85084237797881ea137492bfe070
 - dbbe8e8ed4f852e623775b7bd3aec818cdd03376
 - b9f13d48aa7e2c0652210152b971b21c3c419347
 2023-01-28 16:15:28 +00:00
Sebastien Bourdeauducq 800c12e794 fix resolve_channel_name typing 2023-01-12 16:52:36 +08:00
Egor Savkin d36899b485 firmware: unify RTIO error message format 
Co-authored-by: Egor Savkin <es@m-labs.hk>
Co-committed-by: Egor Savkin <es@m-labs.hk>
 2023-01-09 16:13:42 +08:00
Egor Savkin 6b3fa98d70 add channel names to RTIO errors 
Co-authored-by: Egor Savkin <es@m-labs.hk>
Co-committed-by: Egor Savkin <es@m-labs.hk>
 2023-01-09 12:35:56 +08:00
Egor Savkin 44ef13d1c0 Fix idle/startup_kernel typos in config 
Signed-off-by: Egor Savkin <es@m-labs.hk>
 2023-01-03 09:55:36 +08:00
David Nadlinger 8e0229d265 si5324: crystal_{ref -> as_ckin2} [nfc] 
This makes it clear that by itself, the flag does not
cause the input mux to be changed.
 2022-12-17 01:33:50 +00:00
David Nadlinger 2ddb4d259f Undo most of Si5324 unification (5c054cc901) 
This reverts most of 5c054cc901, as it turns out that
si5324::setup is in fact also used to configure the
chip for operation as a DRTIO satellite.
 2022-12-17 01:31:14 +00:00
David Nadlinger 5c054cc901 Unify Si5324 setup code with main ARTIQ repository [nfc] 
I chose the version from the main repository for two
reasons:
 - Explicitly specifying si5324_ref_input every time would
   not work for the different Kasli/… hardware versions.
 - Having `crystal_ref` as a setting in the configuration
   is misleading if it does not actually activate the crystal
   for use as a reference (but rather does
   `route_crystal_to_ckin2`).

Related m-labs/artiq commits:
 - 740543d4e284245248e3ff838c46505938dcae7a
 - 3c7a394eff553ab75a7ea78bdd17830366504dc6
 2022-12-12 23:22:01 +00:00
Sebastien Bourdeauducq db0e41af6d update zynq-rs and some Rust deps 2022-11-30 22:49:10 +08:00
mwojcik c834e4f503 enable network and mgmt during Rust panic, make RTIO PLL lock failure a panic 
Closes #198 #200

Making it a soft panic makes it more involved with a bit of code duplication - setting up mgmt requires setting up the interface and sockets. Maybe can be done a bit cleaner.

```
[spaqin@hera:~/m-labs/artiq-zynq]$ artiq_sinara_tester
****** Sinara system tester ******
[...]
ConnectionRefusedError: [Errno 111] Connection refused

[spaqin@hera:~/m-labs/artiq-zynq]$ artiq_coremgmt -D 192.168.1.56 log
[     0.000067s]  INFO(runtime): NAR3/Zynq7000 starting...
[     0.005238s]  INFO(runtime): detected gateware: GenericMaster
[     0.016152s]  INFO(libboard_zynq::i2c): PCA9548 detected
[     0.023004s]  WARN(runtime): config initialization failed: SD error: Card initialization error: No card inserted, check if the card is inserted properly.
[     0.036730s]  WARN(runtime::rtio_clocking): error reading configuration. Falling back to default.
[     0.213000s] ERROR(runtime::rtio_clocking): RTIO PLL failed to lock
[     0.224443s]  INFO(libboard_zynq::i2c): PCA9548 detected
[     0.256197s]  INFO(runtime::comms): network addresses: MAC=e8-eb-1b-13-49-8b IPv4=192.168.1.56 IPv6-LL=fe80::eaeb:1bff:fe13:498b IPv6: no configured address
[     0.270183s] ERROR(runtime::comms): There has been an error configuring the device: RTIO PLL failed to lock. Only mgmt interface will be available.
[     4.000095s]  INFO(libboard_zynq::eth): eth: got Link { speed: S1000, duplex: Full }
[    33.148521s]  INFO(runtime::mgmt): received connection
```

Reviewed-on: M-Labs/artiq-zynq#199
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
 2022-10-21 17:56:34 +08:00
mwojcik dc862a9051 match ident message with mainline 2022-10-21 12:08:11 +08:00
mwojcik 19e60073de kasli_soc: ident = variant name 2022-10-21 11:55:24 +08:00
Egor Savkin a546d0f95b Implement reboot for artiq_coremgmt 2022-10-07 18:31:11 +08:00
Sebastien Bourdeauducq d6ae646790 update dependencies 2022-10-07 18:30:39 +08:00
Sebastien Bourdeauducq f3310324d7 update dependencies 2022-08-26 17:37:27 +08:00
Sebastien Bourdeauducq 0812f22423 update dependencies 2022-07-20 17:34:26 +08:00
kk105 b638fce069 update SEEN_ASYNC_ERRORS in destination_survey (#195) 
Co-authored-by: kk105 <kkl@m-kabs.hk>
Reviewed-on: M-Labs/artiq-zynq#195
Co-authored-by: kk105 <kkl@m-labs.hk>
Co-committed-by: kk105 <kkl@m-labs.hk>
 2022-06-20 17:41:08 +08:00
occheung 9ec6a1feab dyld/rebind: support rela generation with nac3ld 2022-06-01 21:27:38 +08:00
occheung 8e144e41de reloc: impl ARM_PREL31 handling 2022-06-01 21:27:38 +08:00
occheung 512b6bac12 reloc: add PC-relative relocation support 2022-06-01 21:27:38 +08:00
occheung e3ed41ff32 fix index table reference type 2022-06-01 18:35:50 +08:00
occheung 97a63ca8d0 dyld: add EXIDX entry type 
The type is just for aesthetic. The interpretation of an index table entry is not our concern.
 2022-06-01 18:33:19 +08:00
occheung f0febe0ee4 change catch type to single reference 2022-05-31 18:26:30 +08:00
mwojcik 7a8f96dbd9 rtio_mgt: use mutex's async_lock 2022-05-25 10:39:06 +08:00
mwojcik 596edb480c cargo: update zynq-rs 2022-05-25 10:37:38 +08:00
mwojcik 4f457d9c24 moninj: log link down at debug level 2022-05-25 10:37:38 +08:00
mwojcik 24df52268e moninj: restructure timeout 
stop logging errors if satellite is unavailable
drtio: don't even send message if link is down
 2022-05-25 10:37:38 +08:00