forked from M-Labs/artiq-zynq
runtime/comms: restart core1 before kernel load.
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@ -26,7 +26,7 @@ log_buffer = { version = "1.2" }
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libm = { version = "0.2", features = ["unstable"] }
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libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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libsupport_zynq = { default-features = false, features = ["alloc_core", "dummy_irq_handler"], git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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libsupport_zynq = { default-features = false, features = ["alloc_core"], git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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libcortex_a9 = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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libasync = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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libregister = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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@ -232,6 +232,7 @@ async fn handle_run_kernel(stream: Option<&TcpStream>, control: &Rc<RefCell<kern
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async fn load_kernel(buffer: Vec<u8>, control: &Rc<RefCell<kernel::Control>>, stream: Option<&TcpStream>) -> Result<()> {
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let mut control = control.borrow_mut();
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control.restart();
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control.tx.async_send(kernel::Message::LoadRequest(buffer)).await;
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let reply = control.rx.async_recv().await;
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match reply {
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@ -0,0 +1,46 @@
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use libboard_zynq::{gic, mpcore, println, stdio};
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use libcortex_a9::{
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asm,
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regs::{MPIDR, SP},
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};
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use libregister::{RegisterR, RegisterW};
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use core::sync::atomic::{AtomicBool, Ordering};
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extern "C" {
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static mut __stack1_start: u32;
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fn main_core1() -> !;
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}
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static CORE1_RESTART: AtomicBool = AtomicBool::new(false);
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#[link_section = ".text.boot"]
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#[no_mangle]
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#[naked]
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pub unsafe extern "C" fn IRQ() {
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if MPIDR.read().cpu_id() == 1 {
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let mpcore = mpcore::RegisterBlock::new();
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let mut gic = gic::InterruptController::new(mpcore);
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let id = gic.get_interrupt_id();
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if id.0 == 0 {
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gic.end_interrupt(id);
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asm::exit_irq();
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SP.write(&mut __stack1_start as *mut _ as u32);
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asm::enable_irq();
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CORE1_RESTART.store(false, Ordering::Relaxed);
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asm::sev();
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main_core1();
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}
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}
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stdio::drop_uart();
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println!("IRQ");
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loop {}
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}
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pub fn restart_core1() {
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let mut interrupt_controller = gic::InterruptController::new(mpcore::RegisterBlock::new());
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CORE1_RESTART.store(true, Ordering::Relaxed);
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interrupt_controller.send_sgi(gic::InterruptId(0), gic::CPUCore::Core1.into());
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while CORE1_RESTART.load(Ordering::Relaxed) {
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asm::wfe();
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}
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}
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@ -2,6 +2,9 @@ use libcortex_a9::sync_channel::{Sender, Receiver};
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use libsupport_zynq::boot::Core1;
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use super::{CHANNEL_0TO1, CHANNEL_1TO0, Message};
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use crate::irq::restart_core1;
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use core::mem::{forget, replace};
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pub struct Control {
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pub tx: Sender<'static, Message>,
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@ -34,5 +37,13 @@ impl Control {
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rx: core0_rx,
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}
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}
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pub fn restart(&mut self) {
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restart_core1();
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let (core0_tx, core0_rx) = get_channels();
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// dangling pointer here, so we forget it
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forget(replace(&mut self.tx, core0_tx));
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forget(replace(&mut self.rx, core0_rx));
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}
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}
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@ -40,6 +40,7 @@ mod panic;
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mod logger;
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mod mgmt;
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mod analyzer;
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mod irq;
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fn init_gateware() {
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// Set up PS->PL clocks
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