forked from M-Labs/artiq-zynq
Updated zc706 dependency and fixed compiler errors.
This commit is contained in:
parent
7caee2bf88
commit
fa00ab211d
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@ -201,7 +201,7 @@ dependencies = [
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[[package]]
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name = "libasync"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#0aa75d3544a2092a0ba6ce689c3f025f22ec30e4"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#b65606f2d02fab273645835a102048b23c3394f7"
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dependencies = [
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"embedded-hal",
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"libcortex_a9",
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@ -213,7 +213,7 @@ dependencies = [
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[[package]]
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name = "libboard_zynq"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#0aa75d3544a2092a0ba6ce689c3f025f22ec30e4"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#b65606f2d02fab273645835a102048b23c3394f7"
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dependencies = [
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"bit_field",
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"embedded-hal",
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@ -237,7 +237,7 @@ dependencies = [
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[[package]]
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name = "libcortex_a9"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#0aa75d3544a2092a0ba6ce689c3f025f22ec30e4"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#b65606f2d02fab273645835a102048b23c3394f7"
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dependencies = [
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"bit_field",
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"libregister",
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@ -252,7 +252,7 @@ checksum = "c7d73b3f436185384286bd8098d17ec07c9a7d2388a6599f824d8502b529702a"
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[[package]]
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name = "libregister"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#0aa75d3544a2092a0ba6ce689c3f025f22ec30e4"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#b65606f2d02fab273645835a102048b23c3394f7"
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dependencies = [
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"bit_field",
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"vcell",
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@ -262,7 +262,7 @@ dependencies = [
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[[package]]
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name = "libsupport_zynq"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#0aa75d3544a2092a0ba6ce689c3f025f22ec30e4"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#b65606f2d02fab273645835a102048b23c3394f7"
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dependencies = [
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"compiler_builtins",
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"libboard_zynq",
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@ -26,7 +26,7 @@ log_buffer = { version = "1.2" }
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libm = { version = "0.2", features = ["unstable"] }
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libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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libsupport_zynq = { default-features = false, git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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libsupport_zynq = { default-features = false, features = ["alloc_core", "dummy_irq_handler"], git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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libcortex_a9 = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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libasync = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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libregister = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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@ -48,9 +48,12 @@ SECTIONS
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.heap (NOLOAD) : ALIGN(8)
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{
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__heap_start = .;
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. += 0x1000000;
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__heap_end = .;
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__heap0_start = .;
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. += 0x800000;
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__heap0_end = .;
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__heap1_start = .;
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. += 0x800000;
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__heap1_end = .;
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} > SDRAM
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.stack1 (NOLOAD) : ALIGN(8)
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@ -2,7 +2,6 @@ use core::fmt;
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use core::cell::RefCell;
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use core::str::Utf8Error;
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use alloc::rc::Rc;
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use alloc::sync::Arc;
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use alloc::{vec, vec::Vec, string::String};
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use log::{info, warn, error};
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@ -126,7 +125,7 @@ async fn handle_run_kernel(stream: Option<&TcpStream>, control: &Rc<RefCell<kern
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control.borrow_mut().tx.async_send(kernel::Message::StartRequest).await;
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loop {
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let reply = control.borrow_mut().rx.async_recv().await;
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match *reply {
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match reply {
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kernel::Message::RpcSend { is_async, data } => {
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if stream.is_none() {
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error!("Unexpected RPC from startup/idle kernel!");
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@ -141,7 +140,7 @@ async fn handle_run_kernel(stream: Option<&TcpStream>, control: &Rc<RefCell<kern
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match host_request {
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Request::RPCReply => {
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let tag = read_bytes(stream, 512).await?;
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let slot = match *control.borrow_mut().rx.async_recv().await {
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let slot = match control.borrow_mut().rx.async_recv().await {
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kernel::Message::RpcRecvRequest(slot) => slot,
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other => panic!("expected root value slot from core1, not {:?}", other),
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};
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@ -155,7 +154,7 @@ async fn handle_run_kernel(stream: Option<&TcpStream>, control: &Rc<RefCell<kern
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} else {
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let mut control = control.borrow_mut();
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control.tx.async_send(kernel::Message::RpcRecvReply(Ok(size))).await;
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match *control.rx.async_recv().await {
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match control.rx.async_recv().await {
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kernel::Message::RpcRecvRequest(slot) => slot,
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other => panic!("expected nested value slot from kernel CPU, not {:?}", other),
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}
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@ -166,7 +165,7 @@ async fn handle_run_kernel(stream: Option<&TcpStream>, control: &Rc<RefCell<kern
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},
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Request::RPCException => {
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let mut control = control.borrow_mut();
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match *control.rx.async_recv().await {
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match control.rx.async_recv().await {
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kernel::Message::RpcRecvRequest(_) => (),
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other => panic!("expected (ignored) root value slot from kernel CPU, not {:?}", other),
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}
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@ -233,9 +232,9 @@ async fn handle_run_kernel(stream: Option<&TcpStream>, control: &Rc<RefCell<kern
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async fn load_kernel(buffer: Vec<u8>, control: &Rc<RefCell<kernel::Control>>, stream: Option<&TcpStream>) -> Result<()> {
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let mut control = control.borrow_mut();
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control.tx.async_send(kernel::Message::LoadRequest(Arc::new(buffer))).await;
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control.tx.async_send(kernel::Message::LoadRequest(buffer)).await;
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let reply = control.rx.async_recv().await;
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match *reply {
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match reply {
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kernel::Message::LoadCompleted => {
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if let Some(stream) = stream {
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write_header(stream, Reply::LoadCompleted).await?;
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@ -1,21 +1,33 @@
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use libcortex_a9::sync_channel::{self, sync_channel};
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use libcortex_a9::sync_channel::{Sender, Receiver};
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use libsupport_zynq::boot::Core1;
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use super::{CHANNEL_0TO1, CHANNEL_1TO0, Message};
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pub struct Control {
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pub tx: sync_channel::Sender<Message>,
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pub rx: sync_channel::Receiver<Message>,
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pub tx: Sender<'static, Message>,
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pub rx: Receiver<'static, Message>,
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}
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fn get_channels() -> (Sender<'static, Message>, Receiver<'static, Message>) {
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let mut core0_tx = None;
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while core0_tx.is_none() {
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core0_tx = CHANNEL_0TO1.lock().take();
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}
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let core0_tx = core0_tx.unwrap();
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let mut core0_rx = None;
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while core0_rx.is_none() {
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core0_rx = CHANNEL_1TO0.lock().take();
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}
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let core0_rx = core0_rx.unwrap();
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(core0_tx, core0_rx)
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}
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impl Control {
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pub fn start() -> Self {
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Core1::start(true);
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let (core0_tx, core1_rx) = sync_channel(4);
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let (core1_tx, core0_rx) = sync_channel(4);
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*CHANNEL_0TO1.lock() = Some(core1_rx);
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*CHANNEL_1TO0.lock() = Some(core1_tx);
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let (core0_tx, core0_rx) = get_channels();
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Control {
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tx: core0_tx,
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}
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}
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}
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@ -9,7 +9,10 @@ use libcortex_a9::{
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enable_fpu,
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cache::{dcci_slice, iciallu, bpiall},
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asm::{dsb, isb},
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sync_channel,
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};
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use libboard_zynq::{mpcore, gic};
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use libsupport_zynq::ram;
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use dyld::{self, Library};
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use crate::eh_artiq;
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use super::{
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@ -138,23 +141,23 @@ pub fn main_core1() {
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enable_fpu();
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debug!("FPU enabled on Core1");
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let mut core1_tx = None;
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while core1_tx.is_none() {
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core1_tx = CHANNEL_1TO0.lock().take();
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}
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let mut core1_tx = core1_tx.unwrap();
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ram::init_alloc_core1();
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gic::InterruptController::new(mpcore::RegisterBlock::new()).enable_interrupts();
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let mut core1_rx = None;
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while core1_rx.is_none() {
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core1_rx = CHANNEL_0TO1.lock().take();
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let (mut core0_tx, mut core1_rx) = sync_channel!(Message, 4);
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let (mut core1_tx, core0_rx) = sync_channel!(Message, 4);
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unsafe {
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core0_tx.reset();
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core1_tx.reset();
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}
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let mut core1_rx = core1_rx.unwrap();
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*CHANNEL_0TO1.lock() = Some(core0_tx);
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*CHANNEL_1TO0.lock() = Some(core0_rx);
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// set on load, cleared on start
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let mut loaded_kernel = None;
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loop {
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let message = core1_rx.recv();
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match *message {
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match message {
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Message::LoadRequest(data) => {
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let result = dyld::load(&data, &resolve)
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.and_then(KernelImage::new);
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@ -213,8 +216,6 @@ pub fn terminate(exception: &'static eh_artiq::Exception<'static>, backtrace: &'
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let mut core1_tx = KERNEL_CHANNEL_1TO0.lock();
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core1_tx.as_mut().unwrap().send(Message::KernelException(exception, &backtrace[..cursor]));
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}
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// TODO: remove after implementing graceful kernel termination.
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error!("Core1 uncaught exception");
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loop {}
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}
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@ -1,5 +1,5 @@
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use core::ptr;
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use alloc::{vec::Vec, sync::Arc, string::String};
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use alloc::{vec::Vec, string::String};
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use libcortex_a9::{mutex::Mutex, sync_channel};
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use crate::eh_artiq;
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@ -12,7 +12,7 @@ mod rpc;
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mod dma;
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mod cache;
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#[derive(Debug)]
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#[derive(Debug, Clone)]
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pub struct RPCException {
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pub name: String,
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pub message: String,
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pub function: String
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}
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#[derive(Debug)]
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#[derive(Debug, Clone)]
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pub enum Message {
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LoadRequest(Arc<Vec<u8>>),
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LoadRequest(Vec<u8>),
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LoadCompleted,
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LoadFailed,
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StartRequest,
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KernelFinished,
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KernelException(&'static eh_artiq::Exception<'static>, &'static [usize]),
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RpcSend { is_async: bool, data: Arc<Vec<u8>> },
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RpcSend { is_async: bool, data: Vec<u8> },
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RpcRecvRequest(*mut ()),
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RpcRecvReply(Result<usize, RPCException>),
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}
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static CHANNEL_0TO1: Mutex<Option<sync_channel::Receiver<Message>>> = Mutex::new(None);
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static CHANNEL_1TO0: Mutex<Option<sync_channel::Sender<Message>>> = Mutex::new(None);
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static CHANNEL_0TO1: Mutex<Option<sync_channel::Sender<'static, Message>>> = Mutex::new(None);
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static CHANNEL_1TO0: Mutex<Option<sync_channel::Receiver<'static, Message>>> = Mutex::new(None);
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static KERNEL_CHANNEL_0TO1: Mutex<Option<sync_channel::Receiver<Message>>> = Mutex::new(None);
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static KERNEL_CHANNEL_1TO0: Mutex<Option<sync_channel::Sender<Message>>> = Mutex::new(None);
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static KERNEL_CHANNEL_0TO1: Mutex<Option<sync_channel::Receiver<'static, Message>>> = Mutex::new(None);
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static KERNEL_CHANNEL_1TO0: Mutex<Option<sync_channel::Sender<'static, Message>>> = Mutex::new(None);
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static mut KERNEL_IMAGE: *const core1::KernelImage = ptr::null();
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@ -1,6 +1,6 @@
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//! Kernel-side RPC API
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use alloc::{vec::Vec, sync::Arc};
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use alloc::vec::Vec;
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use cslice::{CSlice, AsCSlice};
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use crate::eh_artiq;
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@ -14,7 +14,7 @@ fn rpc_send_common(is_async: bool, service: u32, tag: &CSlice<u8>, data: *const
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let mut core1_tx = KERNEL_CHANNEL_1TO0.lock();
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let mut buffer = Vec::<u8>::new();
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send_args(&mut buffer, service, tag.as_ref(), data).expect("RPC encoding failed");
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core1_tx.as_mut().unwrap().send(Message::RpcSend { is_async, data: Arc::new(buffer) });
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core1_tx.as_mut().unwrap().send(Message::RpcSend { is_async, data: buffer });
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}
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pub extern fn rpc_send(service: u32, tag: &CSlice<u8>, data: *const *const ()) {
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@ -32,7 +32,7 @@ pub extern fn rpc_recv(slot: *mut ()) -> usize {
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core1_tx.as_mut().unwrap().send(Message::RpcRecvRequest(slot));
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core1_rx.as_mut().unwrap().recv()
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};
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match *reply {
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match reply {
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Message::RpcRecvReply(Ok(alloc_size)) => alloc_size,
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Message::RpcRecvReply(Err(exception)) => unsafe {
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eh_artiq::raise(&eh_artiq::Exception {
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@ -6,13 +6,15 @@
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#![feature(c_variadic)]
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#![feature(const_btree_new)]
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#![feature(ptr_offset_from)]
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#![feature(const_in_array_repeat_expressions)]
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#![feature(naked_functions)]
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extern crate alloc;
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use core::{cmp, str};
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use log::{info, warn, error};
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use libboard_zynq::{timer::GlobalTimer, devc, slcr};
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use libboard_zynq::{timer::GlobalTimer, devc, slcr, mpcore, gic};
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use libasync::{task, block_async};
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use libsupport_zynq::ram;
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use libregister::RegisterW;
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@ -183,7 +185,8 @@ pub fn main_core0() {
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info!("NAR3/Zynq7000 starting...");
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ram::init_alloc_linker();
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ram::init_alloc_core0();
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gic::InterruptController::new(mpcore::RegisterBlock::new()).enable_interrupts();
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init_gateware();
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info!("detected gateware: {}", identifier_read(&mut [0; 64]));
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@ -34,6 +34,12 @@ SECTIONS
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__bss_end = .;
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} > OCM3
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.heap (NOLOAD) : ALIGN(8)
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{
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__heap0_start = .;
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__heap0_end = .;
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} > OCM3
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.stack1 (NOLOAD) : ALIGN(8)
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{
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__stack1_end = .;
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