forked from M-Labs/artiq-zynq
parent
8e3574080c
commit
5149d37be9
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@ -7,7 +7,11 @@ use core::mem;
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use log::{debug, info, error};
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use cstr_core::CStr;
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use libcortex_a9::{enable_fpu, cache::dcci_slice};
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use libcortex_a9::{
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enable_fpu,
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cache::{dcci_slice, iciallu, bpiall},
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asm::{dsb, isb},
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};
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use libboard_zynq::{
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self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll},
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logger,
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@ -57,6 +61,11 @@ pub fn main_core0() {
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dcci_slice(unsafe {
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core::slice::from_raw_parts(ddr.ptr::<u8>(), ddr.size())
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});
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dsb();
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iciallu();
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bpiall();
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dsb();
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isb();
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// Start core0 only, for compatibility with FSBL.
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info!("executing payload");
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