From 5149d37be9dc2c064646b92f450ee23b0e12baa4 Mon Sep 17 00:00:00 2001
From: pca006132 <john.lck40@gmail.com>
Date: Tue, 14 Jul 2020 17:02:42 +0800
Subject: [PATCH] szl: added cache flush and memory barriers. Resolves #50.

---
 src/szl/src/main.rs | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/szl/src/main.rs b/src/szl/src/main.rs
index 717bac89..34fc7145 100644
--- a/src/szl/src/main.rs
+++ b/src/szl/src/main.rs
@@ -7,7 +7,11 @@ use core::mem;
 use log::{debug, info, error};
 use cstr_core::CStr;
 
-use libcortex_a9::{enable_fpu, cache::dcci_slice};
+use libcortex_a9::{
+    enable_fpu,
+    cache::{dcci_slice, iciallu, bpiall},
+    asm::{dsb, isb},
+};
 use libboard_zynq::{
     self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll},
     logger,
@@ -57,6 +61,11 @@ pub fn main_core0() {
         dcci_slice(unsafe {
             core::slice::from_raw_parts(ddr.ptr::<u8>(), ddr.size())
         });
+        dsb();
+        iciallu();
+        bpiall();
+        dsb();
+        isb();
 
         // Start core0 only, for compatibility with FSBL.
         info!("executing payload");